Your first problem is that you've cross-posted to a slew of groups. I have very little desire to reply to some fool who feels they need to do that.
But not only do you overly cross-post, but you lack comprehension.
Inside the dynamic ram is an array of rows and columns. The refresh is to activate each location in turn, because dynamic memory is not static. It needs to be access in order to keep it's content. Since it's an array, you don't need to go through the full address space, just whatever is specified, the row or column.
To use a simple example, say it's a really small RAM, 8 columns by 7 rows, ie 56 address locations. You have to refresh all those columns each time for a full refresh to happen. If you only had a counter with 7 bits output, one of those columns would never see a refresh, so a significant amount of the memory space would never be refreshed.
So you get one of those new DRAMs with twice as much space, having 9 columns by 7 rows, all of 63 bits. Your old refresh circuit will no longer be good enough, because it has 8 outputs, but you now need 9 bits.
That's what they are all trying to tell you as you spew this thread over a bunch of newsgroups.
The details are specific to the DRAM. Some may require column refresh, some row refresh, and the arrangement of the array will vary. You have to track down the details and then match that.
Michael