...How do they make the channel stand off up to 1.5kV (or more?) in high voltage FETs, yet the gate explodes with less than maybe 100V across it..?
Tim
Device geometry. The gate's withstand voltage is simply determined by the thickness of the insulating oxide layer.
Graham
Yabbut...if that's the case, why can't I run the gate to 1.5kV on a 1.5kVds FET? Why don't they make the insulators thicker for ESD or capacitance reasons eh?
Tim
Because the Vds rating isn't determined by oxide thickness. Besides, who needs a gate rated at 1kV ?
Probably affects the transconductance adversely..
Graham
Well if the channel is a resistor, the potential along it varies smoothly, and there must also be an insulated gate layer on top of it in order to control its conductivity. Thus, the gate insulation *must* increase at the drain end, or there's something you're not telling me. "Geometry" is a rather glib answer...
Tim
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