Hello,
I'm trying to imlpement an USB 1.1 Device on FPGA (Virtex2). Therefore I first used the USB 1.1 Core from Rudolf Usselmann on opencores.org. I got it to enumerate correctly on my Win2K host and I could transmit data through two bulk pipes. But I couldn't solve problems with several lost bytes in the pipes. Also I can't imagine how this core can implement CRC error correction because therefore it would have to delete some data from the external FIFOs it is connected to.
Because of this and other reasons (like better documentation and concept and an easy upgrade to USB 2.0) I'm now trying to use the USB
2.0 core with my USB 1.1 tranceiver. I connected the UTMI lines from the "USB 1.1 PHY" project on opencores to the 2.0 core. Because that didn't work (I think because of the speed negotiation) I replaced the "usbf_utmi_if" modul in the 2.0 core with that from the originally used 1.1 core and added the additional signals. The core and the physical layer are running at 48 MHz and I've adapted the settings in the defines.v at the two relevant positions to 48MHz. Now I can read framenumbers in the Frameregister and find a valid setup packed (GetDevice Descriptor) in the first 8 byte of endpoint 0 OUT buffer. But the buffersize value doesn't change after the reception of the setup packed. My question is has anyone used that core and can tell me, how to detect setup packeds? Will it decrease the buffersize value by 8 or are these packeds indicated in an other way?I have initialized the core with this values: @0x40