Re: An All Digital Phase Lock Loop

My all-digital PLL was similar and worked very well. My reference clock and system clock were pretty stable so I didn't do a lot of analysis. I just designed the loop with a small gain, so it took a bit to lock on (which wasn't a problem in my application) but once it was locked it was very stable and didn't oscillate. The only problem with the low gain is that it took forever to lock in the simulation, so I made an adjustable loop gain so I could kick it up for simulations and see it lock faster (although it rung a bit before locking.)

-Kevin

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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Hi all.

I was actually thinking about digital PLLs recently when I was doing investigation on analog PLLs.

Can someone describe the basic parts and operation of a DPLL? Essentially these are the components I figured would be needed and this is how the operation might work, I'd appreciate comments....

1. Phase / Frequency Detector

Standard two-DFF version, UP/DOWN outputs are used to control a Numerically Controlled Oscillator block.

Input one to the PFD is the signal to be locked onto and input two is the current output(or an ouput controlled by the DPLL), thus UP/DOWN tries to drive the error down. UP/DOWN may have to be sychronized, comments?

A lock signal could be the NAND(UP,DOWN) signals. Thus the output is true when UP and DOWN are both zero.

Though I wonder, since this is a digital system, will 100% lock ever be achieved, thus will the lock signal ever light?.

1. NCO

This block is essentially a mod-N counter which, at the end of it's count, re-loads a count value from a register (perhaps double-buffered). The register("error counter") is setup to increment or decrement it's current value depending on the UP/DOWN signal from the Phase/Frequency detector block.

The mod-N counter is set to count down from the current value, thus, a smaller value in the counter means a higher frequency. This operation (should?) emulate a VCO.

If the counter is configured to count down, I would guess that the "error counter" would have to numerically increment the value it stores when DOWN is true and numerically decrement with UP is true. I reason this because there is an inverse relationship between the value stored in the register and the output frequency (since we're controlling "time" in terms of clock cycles).

1. Gain

The "error" register could be setup to increment by more than decimal 1, perhaps by a power of 2 or something. Maybe even a "coarse" and fine UP/DOWN could be used to get a faster lock.

My guess is that the setup I described emulates a P/I controller since we could control how much the "error register" changes for an UP/DOWN "event", thus this control the "P". And since the "error register" has memory and stores a value even when the system is locked, we have "I".

I'd appreciate any comments on my scheme, what kinds of input clocks I might need, if there are pitfalls and so on. I haven't actually built this, but it's just an idea I've been toying with.

Thanks everyone.

-- Jay.

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I like that idea. Actually, I recalled that mine had a time-varying gain, but it was much simpler. The gain was high before lock, and after locking, the gain switched to something lower. The gain was just implemented by left-shifting the output from the loop filter (which was just a comb or moving-average filter), so the gain could only be powers of two. Does the barrel shifter you describe increase the order of the loop? That probably makes it a lot harder to describe mathematically. I would have liked to do an analysis of mine, but of course I didn't have time, and for my application stability was much more important than lock time so I didn't really have to optimize it.

-Kevin

the

to

number

problem

I like that idea. Actually, I recalled that mine had a time-varying gain, but it was much simpler. The gain was high before lock, and after locking, the gain switched to something lower. The gain was just implemented by left-shifting the output from the loop filter (which was just a comb or moving-average filter), so the gain could only be powers of two. Does the barrel shifter you describe increase the order of the loop? That probably makes it a lot harder to describe mathematically. I would have liked to do an analysis of mine, but of course I didn't have time, and for my application stability was much more important than lock time so I didn't really have to optimize it.

-Kevin

the

to

number

problem

I like that idea. Actually, I recalled that mine had a time-varying gain, but it was much simpler. The gain was high before lock, and after locking, the gain switched to something lower. The gain was just implemented by left-shifting the output from the loop filter (which was just a comb or moving-average filter), so the gain could only be powers of two. Does the barrel shifter you describe increase the order of the loop? That probably makes it a lot harder to describe mathematically. I would have liked to do an analysis of mine, but of course I didn't have time, and for my application stability was much more important than lock time so I didn't really have to optimize it.

-Kevin

the

to

number

problem

I like that idea. Actually, I recalled that mine had a time-varying gain, but it was much simpler. The gain was high before lock, and after locking, the gain switched to something lower. The gain was just implemented by left-shifting the output from the loop filter (which was just a comb or moving-average filter), so the gain could only be powers of two. Does the barrel shifter you describe increase the order of the loop? That probably makes it a lot harder to describe mathematically. I would have liked to do an analysis of mine, but of course I didn't have time, and for my application stability was much more important than lock time so I didn't really have to optimize it.

-Kevin

the

to

number

problem

I like that idea. Actually, I recalled that mine had a time-varying gain, but it was much simpler. The gain was high before lock, and after locking, the gain switched to something lower. The gain was just implemented by left-shifting the output from the loop filter (which was just a comb or moving-average filter), so the gain could only be powers of two. Does the barrel shifter you describe increase the order of the loop? That probably makes it a lot harder to describe mathematically. I would have liked to do an analysis of mine, but of course I didn't have time, and for my application stability was much more important than lock time so I didn't really have to optimize it.

-Kevin

the

to

number

problem

I like that idea. Actually, I recalled that mine had a time-varying gain, but it was much simpler. The gain was high before lock, and after locking, the gain switched to something lower. The gain was just implemented by left-shifting the output from the loop filter (which was just a comb or moving-average filter), so the gain could only be powers of two. Does the barrel shifter you describe increase the order of the loop? That probably makes it a lot harder to describe mathematically. I would have liked to do an analysis of mine, but of course I didn't have time, and for my application stability was much more important than lock time so I didn't really have to optimize it.

-Kevin

Just wondering, I never got any responses to my original (and slightly off-topic) post. Was I off in my design insights? I'm actually thinking about using my aforementioned design in a project, I would like to know if it's a good starting point or not...

One thing I was particularly curious about, when thinking about my own design, do I have to worry about synchronizing / clock domain problems between the two reference inputs to the loop or does the standard two- DFF design actually take care of that?

I'm guessing that the *outputs* (Up/Down) from the DFF loop should be put through a de-metastablizer (two DFF in series or something) since those outputs could change irrespective of my system clock. Comments?

Oh, finally, is there a better frequency/phase detector than the standard two-DFF one? I know that the two-DFF one hunts when the phase/frequency are close to being locked.

Thanks!

-- Jay.

Jasson,

take a look at out free USB 1.1 PHY IP core. It includes a very simple DPLL. It is written in Verilog however.

Best Regards, rudi

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--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759