Open Source Synthesis Tools

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I know there are some open source simulation tools for Verilog and/or VHDL... I can't recall which or if there are simulators for both languages.  I believe there are significant shortcomings in any case.  

I'm pretty sure there is an open source tool for backend place and route and bit stream generation of the Lattice iCE40 devices, well, some of them anyway.  I don't recall what they use for synthesis front end.  

Are there other FOSS synthesis tools for either Verilog or VHDL?  What are the limitations?  


  Rick C.

  - Tesla referral code - https://ts.la/richard11209

Re: Open Source Synthesis Tools
Hello Rick

On 02/02/2019 04:30, snipped-for-privacy@gmail.com wrote:
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There's this ASIC design tools suite from Pierre et Marie Curie  
University in Paris :  
https://www-soc.lip6.fr/equipe-cian/logiciels/alliance/ but it's more  
ASIC-oriented.

Nicolas

Re: Open Source Synthesis Tools
Am 02.02.19 um 04:30 schrieb snipped-for-privacy@gmail.com:
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I guess the most well-known free simulators are GHDL and Icarus Verilog.
Icarus Verilog used to have some synthesis support, but it was dropped.
yosys is a well-known current synthesis tool (targeting Xilinx 7-Series
and Lattice iCE40 and ASIC).
I once used a flow based on Berkely vl2mv, vis, abc, Icarus Verilog to
get to a simulated ASIC from Verilog.

I guess there is a lot more out there.

Philipp

Re: Open Source Synthesis Tools
W dniu sobota, 2 lutego 2019 04:30:52 UTC+1 u?ytkownik gnuarm.del...@g
mail.com napisa?:
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L... I can't recall which or if there are simulators for both languages.  I
 believe there are significant shortcomings in any case.  
Quoted text here. Click to load it
and bit stream generation of the Lattice iCE40 devices, well, some of them  
anyway.  I don't recall what they use for synthesis front end.  
Quoted text here. Click to load it
e the limitations?  
Quoted text here. Click to load it

I think that currently the most successful project is Yosys. It supports La
ttice and Xilinx 7 series FPGAs.
https://github.com/YosysHQ/yosys

There's also very nice frontend for Yosys - SymbiYosys, which can be used f
or formal verification of RTL code. It supports only Verilog in free versio
n, but also VHDL in paid version.
https://github.com/YosysHQ/SymbiYosys

There's also very preliminary VHDL frontend for Yosys based on GHDL:
https://github.com/tgingold/ghdlsynth-beta

Adrian

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