help: buggy IDE driver on Intel IXP425 GPIO(EXPB)

I have to use this ide vhdl driver that's supposed to link an IDE channel to the expansion bus of an IXP425 Intel processor. I asked why they didn't just connect the IDE signals to the GPIO, but they said they needed to adapt to IDE/ATA cycles

Unfortunately, Linux can't recognize newer drives and I see bad behavior in general.

I'm still wondering why they didn't use the opencore PCI driver, since our FPGA is connected also to the PCI bus...

Can anyone help me find any problems?

Thank you, M

Here's the code:

LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all;

ENTITY ide IS

PORT(

-----------------------------------------------------------------------

-- GP Ports

----------------------------------------------------------------------- P_CLK : IN std_logic; -- 1/2 MPC CLKOUT -> 25 MHz P_RESET_N : IN std_logic;

-----------------------------------------------------------------------

-- XScale Bus Port

----------------------------------------------------------------------- P_DB_OUT : OUT std_logic_vector(15 DOWNTO

0); P_DB_IN : IN std_logic_vector(15 DOWNTO 0); P_CS_N : IN std_logic; P_EXPB_RD_N : IN std_logic; P_EXPB_WR_N : IN std_logic; P_EXPB_IOWAIT_N : OUT std_logic; P_EXPB_ADDRESS : IN std_logic_vector(10 DOWNTO 0); P_EXPB_IRQ : OUT std_logic;

-----------------------------------------------------------------------

-- IDE Bus Ports

----------------------------------------------------------------------- P_IDE_DB_OUT : OUT std_logic_vector(15 DOWNTO

0); P_IDE_DB_IN : IN std_logic_vector(15 DOWNTO 0); P_IDE_DIOR_N : OUT std_logic; P_IDE_DIOW_N : OUT std_logic; P_IDE_CS1_N : OUT std_logic; P_IDE_CS3_N : OUT std_logic; P_IDE_DA : OUT std_logic_vector(2 DOWNTO 0); P_IDE_RESET : OUT std_logic; P_IDE_DMACK_N : OUT std_logic; P_IDE_INTRQ : IN std_logic; P_IDE_IORDY : IN std_logic; P_IDE_OE_N : OUT std_logic; P_DBG : OUT std_logic_vector(7 DOWNTO 0) );

END ide;

ARCHITECTURE rtl OF IDE IS

-----------------------------------------------------------------------

-- Custom Type Definitions

----------------------------------------------------------------------- TYPE t_nowdskrd IS (IDLE, S0, S1, S2, S3); TYPE t_nowdskwr IS (IDLE, S0, S1, S2, S3); TYPE t_nowcnt IS (IDLE, S0, S1);

-----------------------------------------------------------------------

-- Signal Type Definitions

----------------------------------------------------------------------- SIGNAL s_nowdskrd : t_nowdskrd; SIGNAL s_nowdskwr : t_nowdskwr; SIGNAL s_nowcnt : t_nowcnt;

-----------------------------------------------------------------------

-- Constants

-----------------------------------------------------------------------

-----------------------------------------------------------------------

-- DIORn/DIOWn Pulse Width: (C_IDEDELAY + 3) * ClockTick(nS) nS

-----------------------------------------------------------------------

--CONSTANT C_IDEDELAY : std_logic_vector(7 DOWNTO 0) := "00001111"; CONSTANT C_IDEDELAY : std_logic_vector(7 DOWNTO 0) := "00000001";

-----------------------------------------------------------------------

-- Signals

----------------------------------------------------------------------- SIGNAL s_clk : std_logic; SIGNAL s_reset_n : std_logic; SIGNAL s_cs_n : std_logic; SIGNAL s_cs1_n : std_logic; SIGNAL s_cs3_n : std_logic; SIGNAL s_da : std_logic_vector(2 DOWNTO 0); SIGNAL s_cntend : std_logic; SIGNAL s_cntstart : std_logic; SIGNAL s_cntrdstart : std_logic; SIGNAL s_cntwrstart : std_logic; SIGNAL s_expb_iowait_n : std_logic;

SIGNAL s_cntdly : std_logic_vector(7 DOWNTO 0); SIGNAL s_ide_dior_n : std_logic; SIGNAL s_ide_diow_n : std_logic; SIGNAL s_idedb_out : std_logic_vector(15 DOWNTO 0); SIGNAL s_idedb_in : std_logic_vector(15 DOWNTO 0);

SIGNAL s_db_out : std_logic_vector(15 DOWNTO 0); SIGNAL s_db_in : std_logic_vector(15 DOWNTO 0); SIGNAL s_expb_wr_n : std_logic; SIGNAL s_expb_rd_n : std_logic; SIGNAL s_expb_addr : std_logic_vector(10 DOWNTO 0);

SIGNAL s_idereg : std_logic_vector(7 DOWNTO 0); SIGNAL s_ide_irq : std_logic; SIGNAL s_decadd : std_logic_vector(1 DOWNTO 0); SIGNAL s_cs_reg_n : std_logic; SIGNAL s_ide_iordy_n : std_logic; SIGNAL s_ideout_latch : std_logic_vector(15 DOWNTO 0); SIGNAL s_ide_oe_n : std_logic;

BEGIN

-----------------------------------------------------------------------

-- Input Port Assign

----------------------------------------------------------------------- s_clk