Global ressource problem

Hi

i'm developping an architecture using Libero and Actel FPGA, i had a problem with global ressources, i had 8 global ressources and the FPGA contains only 6, is there any way to oblige the compiler to not consider some signals as global ressources, synthesysing tool used: Synplify,

regards, A.

Reply to
Amine.Miled
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The simply answer is yes. But first perhaps you can expalin what you want to use the global resources for? If you want 8 clocks for exampe then you will need to consider what Synplify will synthesise instead of a global buffer.

What Actel family are you using?

Alan

Reply to
Alan Myler

The Actel Family that i'm using is FUSION, the chip is AFS600, the problem is when i use a macro to use the internal clock, synplify can syhthesize the architecture but when i do the place and route step the compiler detect an error of extra global ressources.

i need just two clocks as global ressources and there two reset signals that are detected as global rssources which is right but synplify is autodetecting other signals as global ressources (i used the default configuration of synplify, in libero environment)

here the error message i m receiving: Error: CMP601: This design has a CLKSRC instance 'Clock_div_inst/ CLK_inferred_clock/U_CLKSRC' driven by a clock net which is not needed.

i know that in the message it mentioned that "is not needed" but it it is needed!!!!

if yes i can configure synplify to not consider some signal as global ressources and some others as essential global ressources, how can i do it?

Regards,

Reply to
Amine.Miled

Have you looked at the Synplicity FPGA Synthesis Reference Manual section entitled "Designing with Actel?" Specifically, the "Actel Attribute and Directive Summary."

possibly helpful: synthesis syn_global_buffers synthesis syn_noclockbuf synthesis syn_insert_buffer

Reply to
John_H

I'm using Fusion Family and the chip is AFS600, the message provided by the compiler after synplify synthsized the architecture is ERROR: CMP601: this design has a CLKSRC instance 'clock_dif_inst/ CLK_inferred_clock/U_CLKSRC' driven by a clock net wich is not needed. Befor compiling this design, this macro must be removed from the design.

i need this macro so i can t remove it!!!

So if synplify can be reconfigured to consider some signals as essential and others not, how can i do it?

PS: I'm using libero environment with synplify 8.4 i m using default setting,

Regards, Am> snipped-for-privacy@gmail.com wrote:

Reply to
Amine.Miled

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