I need the answer within clock cycles. One clock cycle would be great, although I can bear a few more. I didn't mention that the priority encoder or whatever solution should be parametrizable in VHDL. Just as background information, I'm developing a bus where all modules (DMA, CCD cameras, etc) can request a long write to SDRAM at any moment. Since the transfer is quite long, over 512 words, I don't care if the arbiter takes a few cycles to resolve who will be granted the bus.
I'm trying this now:
signal requests : std_logic_vector(m-1 downto 0); signal resolved : std_logic_vector(m-1 downto 0);
process(i_Clk, i_Rst, first_level) variable found : std_logic; begin if (i_Rst = '1') then resolved '0'); elsif (i_Clk'event and i_Clk = '1') then found := '0'; for y in 0 to m-1 loop if (requests(x) = '1' and found = '0') then resolved