1. Home
  2. Field-Programmable Gate Arrays
  3. approximation of an exponential ramp?

approximation of an exponential ramp?

In an interview from 97, Bob Yannes the designer of MOS 6581 (aka "SID") said the following aboud the chips ASDR enveloper:

"In order to more closely model the exponential decay of sounds, another look-up table on the output of the Envelope Generator would sequentially divide the clock to the Envelope Generator by two at specific counts in the Decay and Release cycles. This created a piece-wise linear approximation of an exponential. I was particularly happy how well this worked considering the simplicity of the circuitry. The Attack, however, was linear, but this sounded fine."

In short, he was using an down-counter to count down from 255 down to some number, but he somehow made the counter to move pseudo-exponentially instead of linearly.

Does anyone know how this works?

burns

(the whole interview is found at

formatting link

Reply to
burn.sir
Loading thread data ...

You could use a table, but that's likely to get large, and you could use a simple binary shift 1/2^n, which will approximate decays, but that's likely to be a bit coarse, (even if very simple) as each change is 2:1.

I'd imagine the best would be a mix of the two. handle the coarse side with binary shifting, /2, and the finer selection between the two with a table, which now only has to cover a 2:1 range, so can be smaller ?

Think of this as a bit like a tiny floating point number format : exponent and mantissa.

-jg

Reply to
Jim Granville

snipped-for-privacy@gmail.com schrieb:

Well, he explains it, doesn't he? "sequentially divide the clock to the Envelope Generator by two at specific counts in the Decay and Release cycles"

So there is a linear down counter, with a clock divider in front. Based on the counter value the clock devider value is increased. In an FPGA you would want to control a clock enable instead of the clock.

Kolja Sulimma

Reply to
Kolja Sulimma

you could implement a decaying exponential using a LUT and to keep the LUT from getting too big, you sample the decaying exponential at just enough points, then linearly interpolate between those points

Say if you wanted to estimate an exponential function with 16 bits of precision, you could sample the function at say 256 equidistant points, then the LUT would have

256 entries with 16 bit word size each.

To get the value of the exponential at a point lying between the 256 you sampled, figure out which two (table entries) you are between and linearly interpolate.

Kolja Sulimma wrote:

Reply to
wallge

That interview is from Aug 1996, about two months before Ensoniq went kerblooey.

-a

Reply to
Andy Peters

You can model a simple exponential decay:

Given integer N in a register, iterate...

N = N - K * N

where K < 1.

One simple value for K is 0.5. So N drops in half every iteration. A little less severe is .25 (right shift 2) or 0.125 (shift 3) etc.

The smaller K, the more this looks like an exponential decay, and the slower it decays. It won't ever get to zero unless you compute to more bits than you actually use, namely throw away some LSB guard bits.

John

Reply to
John Larkin

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.