Baloney. Hot spots don't anneal out, for one thing, and for another, the effect exists at low-milliwatt dissipations. Hot spots are associated with _second_ breakdown, not normal breakdown.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
That's the expectation. The breakdown can occur over the base area, but is more likely (in a transistor designed for non=IC use) to have significant conduction (and E-field) on the surface, and moving ions in that surface layer can poison the BE junction, making it leaky (and high surface doping base majority carriers will hurt beta). In forward bias, the thinnest BE depletion is on the full emitter area, and buried at depth; current is vertical. In reverse bias, the higher doping of the base near the surface means there's more surface (lateral) current.
There's ways to combat the surface currents, though; guard rings and passivation tricks and the like. So, a generic '2N3904' can be expected to do almost anything. The zenering of B-E causing a negative voltage C-B, at low currents, was easy to demonstrate, but hard to use because it didn't repeat very well. One day there'd be -0.34V, the next -0.22V....
I'm not sure why 'plasma' is called a cause of parameter changes, either; IMPATT and TRAPATT diodes (plasma avalanche transit time is the 'PATT' part) were expected to operate normally for decades, and partly that was because they were vertical-breakdown devices, not surface (lateral). Plasma was just a normal-ish electron gas in the solid.
Properly passivated planar Si transistors don't have surface crud problems like that. The oxide is grown and not deposited, so there are few interface states, for one thing. For another, the effect is dramatically faster at higher current, whereas the zener voltage doesn't change much. It really is hot carrier damage and not crud migrating.
"microplasma" is a poor name for an avalanche event. One carrier pair starts it off, and then it grows some and dies away as the carriers reach the contacts or undepleted silicon. It isn't necessarily destructive--you don't usually care about enhanced recombination in a zener diode.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
Getting the correct oscillator amplitude is critical in crystal oscillators. If the amplitude is too high, the oscillator may have excessive drift or the crystal may crack. If the amplitude is too low, the oscillator may fail to start with some crystals.
Pertubation techniques don't always work, especially with high-Q crystals.
If they do work, you still have to wait for the oscillator to start up and reach full amplitude and stabilize. This may take many milliseconds in simulation time. It is virtually impossible to make meaningful measurements of oscillator waveforms at these time delays.
My technique works with zero time delay. This makes it easy to monitor the waveforms and see the effect of different parameters. You can even change the oscillator gain and amplitude and quickly adjust the startup to compensate.
Again, it may be necessary to replace the LTspice.ini file to get the oscillator to run. I have no clue why.
A high Q XO can take a couple million simulated cycles to settle out in amplitude. I set up an initial condition at about my expected amplitude, start it, and see if the swing is increasing or decreasing over maybe 100 cycles; iterate.
Real XO frequency and phase slope analysis has to be done in frequency domain.
But nowadays, I buy XOs. Even super low phase noise ones are cheap. I can usually buy an entire XO or OCXO for less than I can buy the crystal.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
Electro-migration does the damage. Whether you "think" there's not "crud" there matters not. For long term survival don't do it.
Many modern chip processes specify max reverse Vbe wa-a-a-ay below breakdown.
Why this discussion floats to the top of the "bowl" almost annually defies all reason.
Don't reverse bias/DO provide limiting means, it's cheap, stop arguing and get over it. ...Jim Thompson
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Thinking outside the box... producing elegant solutions,
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In the 2N2222A, 2N3904 and 2N4401, V(BR)EBO is measured at 10uA. This is
60uW.I can find no indication of damage in the datasheet or in google. So we assume this does not damage the transistor.
On the other hand, applying 8V reverse bias to the base-emitter junction definitley damages the transistor. So there must be a threshold current below which there is no damage. It seems the only way to find this threshold is to measure the degredation with increasing reverse bias current.
It sounds as if you may be using a variation of my technique which I posted here some time ago. I have since found it may not work with some crystal oscillators due to an anomaly in the LTspice.ini file.
How? The oscillator has positive feedback. This messes up the frequency sweep. The oscillator is highly nonlinear. This means operating in the linear mode during a frequency sweep may give false results. If you break the loop, you are no longer working with the loaded Q of the oscillator.
You can measure the frequency in the time domain to parts per billion resolution.
It depends on your phase noise requirements. This is critical when you have to multiply into the microwave frequencies.
If you make a parallel LC in LT Spice, and goose it to ring, and do the transient analysis, the default setup will show a frequency that is a couple of per cent off. You can, with effort, measure frequency to parts per billion, but the signal that you are measuring is probably wrong.
I don't think it is possible, or possible in one's working lifetime, to accurately simulate a high-Q XO in time domain, to parts per billion frequency accuracy. The time step would have to be attoseconds. You might run out of double-float precision.
Well, buy a better oscillator.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
John Larkin wrote:
You made this claim in July, 2015, and have repeated it several times. You are completely wrong.
You were oblivious to the fact LTspice sets the series resistance of an inductor to 1 milliohm unless you specify otherwise.
I have no clue how you measured the frequency offset. Your DIFF signal cannot tell the difference between a frequency error and a difference in amplitude.
If you plot the IDEAL and LC waveforms on the same graph, it is clear the LC amplitude is decreasing. You need to set the inductor series resistance to zero.
Then, if you set the time step to 100us and set the time step to 1000 seconds, you will measure a time difference in the zero crossings of around
31.68 us after 1000 seconds. This is 31.68 parts per billion. This is much more accurate than any component you can buy.Here is your post:
LT Spice LC Simulation
John Larkin
7/26/15This is fun. The LC should ring at 1 Hz, but in the default Spice sim, it's low by about 1800 PPM. You have to crank the time step down to 10 us to get the error down below 10 PPM, and the sim gets really slow. Which illustrates the futility of trying to do accurate sims of high-Q circuits in the time domain.
Version 4 SHEET 1 880 680 WIRE 224 -192 64 -192 WIRE 416 -192 224 -192 WIRE 480 -192 416 -192 WIRE 64 -112 64 -192 WIRE 416 -112 336 -112 WIRE 480 -112 416 -112 WIRE 336 -80 336 -112 WIRE 224 -64 224 -192 WIRE 288 -64 224 -64 WIRE 288 -16 224 -16 WIRE 64 16 64 -32 WIRE 336 32 336 0 WIRE 224 112 224 -16 WIRE 224 112 64 112 WIRE 320 112 224 112 WIRE 416 112 320 112 WIRE 480 112 416 112 WIRE 64 160 64 112 WIRE 320 160 320 112 WIRE 224 176 224 112 WIRE 64 288 64 240 WIRE 224 288 224 240 WIRE 320 288 320 240 FLAG 224 288 0 FLAG 320 288 0 FLAG 64 288 0 FLAG 64 16 0 FLAG 336 32 0 FLAG 416 -112 DIFF FLAG 416 -192 IDEAL FLAG 416 112 LC SYMBOL ind 304 144 R0 WINDOW 0 47 100 Left 2 WINDOW 3 -2 185 Left 2 SYMATTR InstName L1 SYMATTR Value 0.159154943 SYMBOL cap 208 176 R0 WINDOW 0 29 70 Left 2 WINDOW 3 -73 154 Left 2 SYMATTR InstName C1 SYMATTR Value 0.159154943 SYMBOL current 64 160 R0 WINDOW 0 -70 50 Left 2 WINDOW 3 -165 99 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName I1 SYMATTR Value PULSE(1 0 1) SYMBOL voltage 64 -128 R0 WINDOW 0 -109 61 Left 2 WINDOW 3 -188 104 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value SINE(0 1 1 1) SYMBOL e 336 -96 R0 WINDOW 0 60 40 Left 2 WINDOW 3 53 74 Left 2 SYMATTR InstName E1 SYMATTR Value -100 TEXT -208 80 Left 2 !.tran 0 25 0 TEXT -272 -176 Left 2 ;LT Spice LC Simulation TEXT -232 -136 Left 2 ;JL July 2015
set the stop time to 1000 seconds
I did say "default setup."
But to sim an XO in time domain, to PPB resolution, you'd have to wait for days. Or maybe years.
I can buy a fabulous OCXO for $70, less than I can buy a raw SC-cut crystal for.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
Dangerous assumption. Data sheets too often fail to confess all.
I did some analogous measurements of a BCX70, specifically b-e zener voltage vs time. Tens of maH changed the junction quite a bit.
I've looked for serious studies of beta degradation vs integrated be- zener charge but never found anything good.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
Hot carrier degradation is seen in MOSFETs and in germanium-silicon heterojunction npn bipolar devices and in polysilicon base npn transistors. The 2N3904 does not appear to be in one of those categories. So even though the ranking expert in this chat room says no good was found, he shows no proof of silicon npn degradation or pnp silicon bipolar devices. Until a document is provided, I doubt any damage from hot carrier injection into bulk silicon. MOSFET damage is at a surface. Poly bases are at a surface. Ge-Si heterojunctions are at a surface. 2N3904 is probably a bulk silicon device with no such surfaces. Rejoice!
Back a few years ago, the Apollo mission had problems with the uA709s ("W" stepping); "ionic contamination". Tests at Fairchild Semi determined the actual problem was due to zenering the differential input at burn-in (data sheet schematic was NOT used, the burn-in circuit managed to repetitively put a 2V stress across the inputs). The damage could be easily annealed out, which would restore the beta and reduce the input current(Ios). Over a range from nanoamps to microamps (do not remember how much), it acted like radiation damage: dosage VS time.
Perhaps a paper was written up with graphed data; that would certainly put a definitive "bent" to this discussion.
Light from reverse-biased base-emitter junction (6V 100mA)
I wouldn't assume that at all. Running any device at abs max is liable to hurt its lifetime, and the physics of the problem is more or less a Poisson process. Of course there's also the true (tunnelling) Zener effect, which doesn't damage the silicon, and which may dominate at very low currents if the breakdown voltage is in the < 7V range, which it often is.
That would be good, of course.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
This is well known; LEDs before preset ones. Only documentation seen at HIGH base zener current. AFAIK nobody has tried to observe LIGHT at low currents (under 1mA).
Infrared (deep red visible) light from zener diode 27v
Visible white light dot from 7812 ( lower left corner) Forward bias junction = infrared light
High voltage bipolar transistor Forward bias junction base-collector
Military russian "7805"
infrared light emitted during programming EPROM
IMHO, zener diodes fail at operation on a microcurrent.
Taking pictures with a DRAM chip:
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