Could some electronics guru please clarify the following ? A MOSFET(N/P-MOS) is a symmetrical about the gate, i.e., if in a circuit the drain and source pins are interchanged, the circuit behavior would not change. So why do textbooks and related literature denote the source node with an arrow ? Same argument holds for a BJT, be it a NPN or a PNP, the device is symmetrical about the base. Or is it the case that duping levels for the two symmetrical nodes in both the above cases are different -- resulting in asymmetry ?
Nope. There are a few BJTs out there as well as a few JFETs that will act t he same if the source/drain or collector/emitter are reversed but they are few and far between.
No MOSFET acts like that, even a depletion mode. I am not sure about VFETs but they are not very common either.
Also, in a MOSFET you cannot do reverse polarity because it has an internal diode that prevents it. It is inherent in the design.
With a JFET, most are not symmetrical because the gate will be placed close r to the source for a few reasons, not the least of which is to avoid drain to gate capacitance if nothing else. With BJTs, the collector does the dis sipation even though the emitter handles more current. As such the collecto r is more tightly coupled to the case and thus the heatsink. And the optimi zation of the whole thing has made it so the emitter and collector are quit e different, maybe even doped differently. If not, you would be screwing wi th transistors with hfe like 20, instead of 2,000 and frequency response in the KHz instead of the GHz.
When you come across an American or European transistor with the base in th e middle it can be hard to ID the pinout with a meter. Smart transistor tes ters do it by keeping the operating voltage below the avalanche point of mo st B-E junctions and actually determining with way has more gain. It will a lways have less gain the wrong way.
you might actually be able to still get JFETs and BJTs that behave the same both ways, but they will be hard to find, and ... ... ... WHY ? You would be hard pressed to find a circuit topology that needs that or would benefit by it. I am sure there is something out there and some smartass might just pop in and tell us about one, but that is going to take some looking. Even using them for analog signal gain control, you simply do not need that fea ture.
I would like to see the circuit that does. (yes, I am goading the peanut ga llery here lol)
the same if the source/drain or collector/emitter are reversed but they ar e few and far between.
BJT's worked as inverted transistors if you treat the collector as an emitt er and the emitter as a collector. The current gain is usually a lot lower in the inverted mode, but the "collector" saturation voltage can be a lot l ower. One circuit I worked exploited just that effect.
Most JFETs are perfectly reversible.
s but they are not very common either.
al diode that prevents it. It is inherent in the design.
ser to the source for a few reasons, not the least of which is to avoid dra in to gate capacitance if nothing else.
When I last looked, that was rare and unusual.
The National Semiconductor Discrete Semiconductor Devices data book lists 1
8 JFET process characteristics, with layout diagrams. Pretty much all of th em show drain and source metallisations to be essentially symmetrical.
dles more current. As such the collector is more tightly coupled to the cas e and thus the heatsink. And the optimization of the whole thing has made i t so the emitter and collector are quite different, maybe even doped differ ently. If not, you would be screwing with transistors with hfe like 20, ins tead of 2,000 and frequency response in the KHz instead of the GHz.
the middle it can be hard to ID the pinout with a meter. Smart transistor t esters do it by keeping the operating voltage below the avalanche point of most B-E junctions and actually determining with way has more gain. It will always have less gain the wrong way.
me both ways, but they will be hard to find, and ... ... ... WHY ? You woul d be hard pressed to find a circuit topology that needs that or would benef it by it. I am sure there is something out there and some smartass might ju st pop in and tell us about one, but that is going to take some looking. Ev en using them for analog signal gain control, you simply do not need that f eature.
** So I have often heard, but never come across any product where the maker's pin designations were not strictly followed.
One unusual app I have seen is using the G-S junction as a low leakage diode - usually protecting another JFET's gate at the input of a scope's vertical amplifier.
I think the Korg MS-20 synthesizer from the late 1970s used the intrinsic resistance of the base-collector junction of some BJTs in inverted mode as the variable resistance elements in its voltage-controlled filter...
Some manufacturers (eg. specifically state that the S & D are interchangable.
--sp
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Some _mixed_ voltage processes, say a chip with 3.3V, 5V, and 30V devices, will have a definite orientation for D-G-S, because the drain is "extended" with addition implants to allow it to stand off higher voltages.
I am bound by NDA's so I can not show any examples. ...Jim Thompson
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| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
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I love to cook with wine. Sometimes I even put it in the food.
the middle it can be hard to ID the pinout with a meter. Smart transistor t esters do it by keeping the operating voltage below the avalanche point of most B-E junctions and actually determining with way has more gain. It will always have less gain the wrong way.
I may well be wrong here, I thought some rf transistors were deliberately l ower gain than when ivnerted to reduce miller.
True, but those make simple low part count LED flashers!
One must remember to not zener the emitter using a inverted method to obtain low sat voltages. In such cases it is wise to place a zener on the output or some sort of over voltage suppressor.
The correct symbol for a fet or mosfet does not place an arrow in the source, The arrow in source is a laziness for simple minded folk who think in terms of bjts and so need the reminder that an n-channel mosfet conducts when the gate is driven positive in the same way as an npn bjt turns on when the base is positive.
The incorrect arrow in source symbol is dangerous because the arrow is the opposite direction to the correct symbol which has the arrow to/from the body substrate. In descrete mosfets the body is often connected to the source terminal so the arrow direction then becomes a helpful reminder of the body diode polarity. The arrow in source notation does not describe the device physics in the same way as the correct symbol does.
I argue with the zeal of an ex-smoker or ex-drinker, for I too once drew mosfets with arrows in the source. Then I had to mix depletion mode mosfets, jfets and enhancement mode mosfets in one drawing and learnt to love the clarity of the solid channel versus dashed channel of the correct notation and the way it makes a mosfet look like a jfet and not like a bjt.
Symbols are for human understanding, all that matters is that devices netlist properly, so that a chip gets correct layout and processed properly...
I build all my own symbols, mostly to ensure I don't miss a required connection (which can be obscure with modern chip processes), and get orientation right in an HV situation... a wrong-side-up HV device will be an instant fry >:-} ...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
We do B-sized schematics so we can print them on a digital copier. Adding enough doodads to distinguish enhancement and depletion, and show the substrate diode, and whatever, makes a small symbol too busy.
I find that I can better visualize current flow and general circuit functions with the symbol that we use. Of course, current flows from top to bottom, so PNP emitters and p-fet sources are up.
There are all sorts of goofy mosfet symbols in use. One that I especially dislike is just a step in a wire, with a gate, no hint of what's the source or drain. Some people make it worse by adding a bubble at the gate if it's p-channel. IC designers seem to like that one.
formatting link
Schematics are art, important art, so this matters.
The conventional symbol shows the presumed substrate diode hitting the middle of the insulated channel, which isn't right. Some people add the substrate diode as a separate diode parallel to the channel, which is correct but awfully busy. I know there's a substate diode so I don't have to draw it.
I like an nfet to look like an insulated-gate NPN transistor, arrow pointing away from the body. So that's the way I (and H+H) draw it. The other symbols take too much thinking and slow me down.
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John Larkin Highland Technology, Inc
lunatic fringe electronics
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Authority doesn't matter if you're right. (I bet you think Obama's right just because he's President, too.)
Typographically speaking, I am infinitely disappointed that they used the not just incorrect but erroneous choice.
There is no such thing as a substrate with an arrow coming straight out; at best it would represent something like an IG-UJT (which is nonsense), or an IGBT, but that has much more structure to it.
The shapes and lines and arrows in a semiconductor symbol do have meaning and order; flouting that only creates confusion. It might save a few strokes when drawing by hand, in much the same way as cursive versus print characters are used in English, but such is not only moot in printed form, but typographers always prefer the more ornate variety (analogous to serif over sans, and in turn, sans over cursive).
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