I have one of these parallel SRAM chips:
I've never interfaced to a chip like this before so looking for some pseudocode/examples of how to set up reads and writes to this from a uP.
I'd like to use the uP just to perform "bank switching" the most significant bits of the address lines; the LSBs indexing into blocks of say 64 1 byte cells will be addressed by a binary counter (it's doing a DDS-kind of thing.)
The uP will need to set up the control and address lines to write data into any arbitrary cell accessible within the address space available with the 4 bit LSB counter paused in whatever state it's in, and change the "banks" for readout similarly, but readout will be driven by external clock/counter and into other stuff, not back onto the uP's bus for reading by that particular uP.
I know i2c and SPI SRAMs are available and so forth, humor me please. :-)