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JFETs being phased out?

Following some remarks here recently about the difficulty in sourcing discrete JFETs I did a bit of searching and discovered to my chagrin that they have indeed become exceedingly rare beasts. I like to breadboard a lot of stuff in discretes for the hell of it, so am mortified at the prospect of the JFET disappearing from the supply chain. Now, Farnell in the UK still has some of these - probably EoL - going cheap:

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But they're optimised for switching. What chance they could be, given careful biasing, re-purposed as amplifiers? Or would the nature of their transconductance curves make that idea a non-starter? Your thoughts invited.

Reply to
Cursitor Doom
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Every J-FET has the same transconductance curve, expressed int terms of pin ch-off voltage, Vp and Idss

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They made bigger and smaller, and with higher and lower pinch-off voltages but that's pretty much it.

The National Semiconductor Discrete Semiconductor Products Databook lists 1

8 different JFET process characteristics, essentially with more or less int er-digitation to give you more or less channel area, and those with more ch annel area are aimed at the switching market.

The J112 is process 51, with a high Idss. It's sold under a heap of other p art numbers, presumably mostly with selected pinch-off voltages, since the process gives you anything from -0.5V to -9.0V, with a typical of -4.5V .

Element1 14 in Australia lists 182 different JFET parts, some of them with a few thousand in stock. You may need to look a bit harder before you panic .

--
Bill Sloman, Sydney
Reply to
bill.sloman

If you're OK with ordering from Thailand or wherever the hell these guys are, they've got enough available of several audio types in TO-92 packages for an entire lifetime if you want to stock up:

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Reply to
bitrex

FWIW I've ordered some stuff from them before, TL431s and op-amps and such and the product has always seemed legit to the level of scrutiny I'm able to apply. YMMV, no commercial affiliation.

Reply to
bitrex

I would be interested in obtaining some of these too. I also have a question about the parameter IDSS. The datasheets quote a figure for IDSS of - say for example - "30mA*" The asterisk states that the test was carried out by pulsing the D-S channel for less than 300uS at a duty cycle of around 2%. Does this imply that you shouldn't run a JFET continuously at levels approaching IDSS for fear it will blow? If so, how do you know what the maximum safe level for continuous quiescent ID is, since it's not quoted in the datasheets?

Reply to
Chris

The problem is almost always simple power dissipation, and that information is listed in the datasheet.

JFETs aren't high current devices, and you aren't going to put enough current through them to move the metalisation around, or create high-current hot-spots in the channel.

--
Bill Sloman, Sydney
Reply to
bill.sloman

Specified at VDS=15V, so it's a _power_dissipation_ limit. PLUS IDSS is temperature dependent, so a pulse test avoids the temperature rise effects. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| STV, Queen Creek, AZ 85142    Skype: skypeanalog |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 

             I'm looking for work... see my website.
Reply to
Jim Thompson

ON Semi just introduced half a dozen new ones. It's the TO-92 that's going away.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

Thanks! So it's okay to run drain current of up to IDSS provided the power rating of the device is not exceeded?

Reply to
Chris

Yes. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| STV, Queen Creek, AZ 85142    Skype: skypeanalog |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 

             I'm looking for work... see my website.
Reply to
Jim Thompson

I sometimes use JFETs enhanced a bit (i.e. I_D > I_DSS), to get more transconductance (and so lower noise) without too much gate current. I can usually stand a few nanoamps' worth, but you have to be careful about temperature variations then.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

Lots of similar things are measured in pulse mode, to avoid self-heating that would bend the curves. The power limits of the part are a separate issue.

Jfets will be power limited, not drain current limited. They limit their own drain current pretty well.

Warning: you can calculate an operating point that is safe from a power dissipation standpoint, but keep the drain voltage low: even modest drain voltages can cause impact-ionization gate current. See AoE3 p 164. If you need more voltage, cascode it or something.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

Right. So the next obvious question that springs to mind is by what mechanism is their drain current self-limiting?

Reply to
Chris

Beats me: that's semiconductor physics.

Jfets enhance a bit, but you can't drive the gate very far positive, or you'll blow it out, so the available enhancement is small. Besides, you are generally using a jfet because you want small gate current.

Phemts enhance a lot more, like 2x Idss, and conduct even more drain current as the gate begins to conduct.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

Lately I've been using J113's for audio amplifiers, they're clean (much better than bipolar in an equivalent circuit) and quiet enough for high-gain overdrive pedals. Typically for a 9V app I use

2.2M/470K to bias the gate with 47K drain and source resistors, bypassing the source with a 2.2K in series with a 10uF to give a gain of ~20 or so. This arrangement minimizes the impact of the +/0.5V typical variability of the needed gate bias but as usual grading/trimming might be needed for perfection. (but distortion pedals typically don't need to be perfect:)

LTspice's 2N4393 model seems very close to a J113.

Wasn't aware that "optimized for switching" makes any difference when using as a linear amp. But yea TO92 everything seems to have numbered days, eventually will all be SMT.. MMBFJ305 seems to be about the same thing. Digikey has thousands of J113 TO92 in 2 different variants (both Fairchild) but can't tell if identical - the datasheet for one with the most stock is password-protected (WTF? nice way to sell parts).

Terry

Reply to
Terry Newton

"Generally" carrier mobility goes down as temperature goes up (at least in Silicon). ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| STV, Queen Creek, AZ 85142    Skype: skypeanalog |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 

             I'm looking for work... see my website.
Reply to
Jim Thompson

You can think of a FET as being made up of a whole lot of little FETs in series (drain to source), with their gates connected together. Drain current causes a voltage drop along the channel of each one, so as you go up the stack towards the drain, V_GS of each one moves in the direction of pinchoff (more negative for an NFET). That applies feedback that holds the overall drain current vaguely constant.

It's a lot squishier than a BJT, though.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

I may well be wrong, but ISTR that a depletion layer can be 'pulled' out from the gate by a high drain voltage alone if it's sufficiently high enough. This layer throttles the current in the same way as if you had applied a negative voltage to the gate terminal. But I can't be 100% sure and might be talking bollocks (and I'm sure someone will point that out if it's the case. :-)

Reply to
Cursitor Doom

I think I'll have that printed on a T-shirt - would have saved me a lot of looooong conversations over the years...

Reply to
JM

I'm an engineer. I don't have to understand it, I just have to make it work.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

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