BF862s are pretty good for that--their transconductance is so high that they go from completely off to I_DSS in about 400 mV. Also I_DSS is pretty tightly specified for a FET, 10 mA < I_DSS < 25 mA.
None of this MPF102-ish stuff. (The Fairchild MPS102 datasheet specifies that at I_D = 200 uA, V_GS is somewhere between -0.5 and -7.5 V. Nice of them.)
An enhancement pHEMT such as an ATF54143 might be a good sub.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Standard technique for linearizing a JFET resistive divider is to add 1/2 t he AC portion of the drain voltage to the DC gate gain- control voltage (yo u probably already knew this!). The large-signal performance is still prett y crappy, the log-anti-log technique works better but takes more components unless you use an IC. Not sure if this would also work for enhancement-mo de.
Bob
Oh yes, I knew it. I am not quite sure now (almost 20 years after my initial design) why I could not use it but I remember I considered and may be tried it. I think the effect kicked in at larger amplitudes than I used (about 100mV IIRC is what I used, in that ballpark anyway), and it did not combine well with the paring for compensation (soldering the cans shorts the gates so one had to live with that).
Yes, large signal was out of question. So they had to be low-noise, the opamps also had to be very quiet (ADI still make them!). Overall things were not as quiet as they nowadays are but it was OK, well below 2 channels FWHM at 8k spectrum from the pulser (nowadays things are well below 1 channel and less mad from the analog point of view - the madness went mostly digital :D...
Dimiter
------------------------------------------------------ Dimiter Popoff, TGI
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Negative supply not needed, just use a P-channel JFET so channel can be grounded, gate positive for max gain, near ground for minimum gain.
The following is a LTSPICE circuit for a simple unity-gain limiter that runs from a single 5V supply and limits the output to about
0.7V RMS. Not super-low distortion when limiting but good for reducing signals to power amps to protect speakers, etc. R16 sets the limited output level, R8 sets overall gain (and input resistor R1 too but don't go too low there), R13 sets attack time, R14 along with R15+R16 sets release time, C4 affects both attack and release. R19 and C6 are special sauce to (attempt) to clean up the attack. A J177 or J176 should work for the JFET (mostly compensates for varying gate threshold.. for more compensation reduce R18 to 4.7K to increase control loop gain but then the special sauce gets trickier), R4 and C5 feeds in the 1/2 channel distortion cancel signal to the emitter of the control transistor, about 1/2 of R17 minus a bit to compensate for gain loss in the transistor. Any decent dual opamp will do.. LT1366 used for convenience. Push-pull config used to detect both positive/negative peaks.The 2nd to last line is a JFET model, probably will wrap so unwrap it (TEXT lines need to be one line).
- Terry
Version 4 SHEET 1 880 680 WIRE 64 -320 32 -320 WIRE 432 -320 64 -320 WIRE 560 -320 432 -320 WIRE 560 -304 560 -320 WIRE 64 -288 64 -320 WIRE 208 -256 192 -256 WIRE 304 -256 288 -256 WIRE 320 -256 304 -256 WIRE 464 -256 400 -256 WIRE 352 -192 272 -192 WIRE 432 -192 432 -320 WIRE 432 -192 352 -192 WIRE 560 -192 560 -224 WIRE 352 -176 352 -192 WIRE -496 -160 -544 -160 WIRE -432 -160 -496 -160 WIRE -320 -160 -352 -160 WIRE -256 -160 -320 -160 WIRE -176 -160 -256 -160 WIRE -80 -160 -176 -160 WIRE -64 -160 -80 -160 WIRE 144 -160 0 -160 WIRE 256 -160 144 -160 WIRE 304 -160 304 -256 WIRE 320 -160 304 -160 WIRE 144 -144 144 -160 WIRE 464 -144 464 -256 WIRE 464 -144 384 -144 WIRE 512 -144 464 -144 WIRE 624 -144 512 -144 WIRE 720 -144 688 -144 WIRE -176 -128 -176 -160 WIRE 256 -128 256 -160 WIRE 320 -128 256 -128 WIRE -544 -112 -544 -160 WIRE -320 -112 -320 -160 WIRE 720 -112 720 -144 WIRE -80 -96 -80 -160 WIRE 464 -96 464 -144 WIRE 352 -80 352 -112 WIRE -224 -64 -256 -64 WIRE 64 -48 64 -208 WIRE 144 -48 144 -64 WIRE 144 -48 64 -48 WIRE 192 -48 192 -256 WIRE 192 -48 144 -48 WIRE -256 -32 -256 -64 WIRE 64 -32 64 -48 WIRE 144 -32 144 -48 WIRE -544 0 -544 -32 WIRE -320 0 -320 -32 WIRE -176 0 -176 -32 WIRE 464 0 464 -16 WIRE 464 0 304 0 WIRE 720 0 720 -32 WIRE 464 16 464 0 WIRE 272 48 272 -192 WIRE 352 48 272 48 WIRE 512 48 512 -144 WIRE 528 48 512 48 WIRE 624 48 592 48 WIRE 64 64 64 48 WIRE 144 64 144 32 WIRE 352 96 352 48 WIRE 32 112 32 -320 WIRE 304 112 304 0 WIRE 320 112 304 112 WIRE 464 128 464 96 WIRE 464 128 384 128 WIRE 528 128 464 128 WIRE 624 128 624 48 WIRE 624 128 592 128 WIRE 192 144 192 -48 WIRE 320 144 192 144 WIRE 624 160 624 128 WIRE 352 192 352 160 WIRE -256 208 -256 48 WIRE -176 208 -256 208 WIRE 32 208 32 192 WIRE 32 208 -176 208 WIRE 32 224 32 208 WIRE 192 224 160 224 WIRE 288 224 272 224 WIRE 528 224 352 224 WIRE -80 240 -80 -16 WIRE 160 272 160 224 WIRE 160 272 96 272 WIRE 320 272 160 272 WIRE 368 272 320 272 WIRE 528 272 528 224 WIRE 528 272 448 272 WIRE 624 272 624 240 WIRE 624 272 528 272 WIRE 320 288 320 272 WIRE 528 288 528 272 WIRE 624 288 624 272 WIRE -80 336 -80 304 WIRE 32 336 32 320 WIRE 32 336 -80 336 WIRE 32 352 32 336 WIRE 320 400 320 368 WIRE 528 400 528 368 WIRE 624 400 624 352 WIRE 32 448 32 432 FLAG -176 0 0 FLAG -320 0 0 FLAG -544 0 0 FLAG 64 64 0 FLAG 144 64 0 FLAG 352 -80 0 FLAG 352 192 0 FLAG 720 0 0 FLAG 560 -192 0 FLAG 528 400 0 FLAG 624 400 0 FLAG 320 400 0 FLAG 32 448 0 FLAG -496 -160 input FLAG 720 -144 output FLAG -256 -160 channel FLAG -176 208 cv SYMBOL res -448 -176 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 100k SYMBOL res -336 -16 M180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R2 SYMATTR Value 12k SYMBOL pjf -224 -128 R0 SYMATTR InstName J1 SYMBOL res -272 -48 R0 SYMATTR InstName R3 SYMATTR Value 10k SYMBOL voltage -544 -128 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value SINE(0 2 200 1 0 0 100) SYMBOL res -96 -112 R0 SYMATTR InstName R4 SYMATTR Value 390k SYMBOL cap -64 -176 M90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 1u SYMBOL res 48 -304 R0 SYMATTR InstName R5 SYMATTR Value 10k SYMBOL res 48 -48 R0 SYMATTR InstName R6 SYMATTR Value 10k SYMBOL cap 128 -32 R0 SYMATTR InstName C2 SYMATTR Value 47u SYMBOL res 128 -160 R0 SYMATTR InstName R7 SYMATTR Value 100k SYMBOL Opamps\\LT1366 352 -208 R0 SYMATTR InstName U1 SYMBOL Opamps\\LT1366 352 64 R0 SYMATTR InstName U2 SYMBOL res 416 -272 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R8 SYMATTR Value 100k SYMBOL res 304 -272 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R9 SYMATTR Value 10k SYMBOL res 480 0 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R10 SYMATTR Value 22k SYMBOL res 480 112 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R11 SYMATTR Value 22k SYMBOL cap 688 -160 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C3 SYMATTR Value 1u SYMBOL res 704 -128 R0 SYMATTR InstName R12 SYMATTR Value 100k SYMBOL voltage 560 -320 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value 5 SYMBOL diode 528 144 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D1 SYMATTR Value 1N4148 SYMBOL diode 528 64 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D2 SYMATTR Value 1N4148 SYMBOL res 608 144 R0 SYMATTR InstName R13 SYMATTR Value 100 SYMBOL cap 608 288 R0 SYMATTR InstName C4 SYMATTR Value 1u SYMBOL res 512 272 R0 SYMATTR InstName R14 SYMATTR Value 10meg SYMBOL res 464 256 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R15 SYMATTR Value 4.7meg SYMBOL res 336 384 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R16 SYMATTR Value 1.5meg SYMBOL npn 96 224 M0 SYMATTR InstName Q1 SYMATTR Value 2N3904 SYMBOL res 16 96 R0 SYMATTR InstName R17 SYMATTR Value 220k SYMBOL res 16 336 R0 SYMATTR InstName R18 SYMATTR Value 10k SYMBOL cap -96 240 R0 SYMATTR InstName C5 SYMATTR Value 1u SYMBOL res 288 208 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R19 SYMATTR Value 330k SYMBOL cap 352 208 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C6 SYMATTR Value 47p TEXT -544 552 Left 2 !* J177\n.MODEL PCHANFET PJF(VTO=-1.8 BETA=3.37432E-3 LAMBDA=2.41676E-2\n+ RD=1.4588 RS=1.4588 IS=7.27555E-16 CGS=8.9E-12\n+ CGD=1.025E-11 PB=6.94243E-1 FC=5E-1) TEXT -560 64 Left 2 !.tran 5
Terry - that comes close but, though the gate is within the available voltage supply, it is backwards relative to the available control direction; ie, positive for lower resistence, negative for greater.
Hul
Terry Newt> > The need for a negative supply or convoluted control circuitry for jfets
Transistors are super-cheap.. and great for feeding in the needed
1/2 channel signal through the emitter to cancel distortion. Actually, for a P-channel FET, more positive is more resistance so if used in a shunt configuration, more gain. If the gain control doesn't have to be fast, here's a simple circuit that provides a simple voltage input for setting gain...input >---100K----*-----------*----------> output | | 1meg | | | 0.022u | | |--' control >--1meg---*------
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