Hopefully one last query

In the days of DEC minicomputers, one had a
Programmer's Card which showed all the instructions
in their binary form. (I've still a couple for
the PDP11 in the archive somewhere)
Is there such a summary available for the 64 bit
instruction set of the Pi3's A53 processors?
My language project, interactive development
along the lines of BASIC but with the speed of
compiled code relies on detailed knowledge of
the instruction set coding; any language needs
an unambiguous form of source code, and why should that
not be the object code itself (with attached symbol
info)?
Reply to
Gareth's Downstairs Computer
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Computer ha scritto:
it's an ARM, so at
formatting link
you'll find all the info you need.
Bye Jack
Reply to
jack4747
formatting link
Reply to
Theo
Not so, for I have all the A53 manuals (one of them at 5000+ pages) but not the programmers card.
Reply to
Gareth's Downstairs Computer
Thanks, I'll browse later when I've worked out how to "unzip" a tar file on windows.
Reply to
Gareth's Downstairs Computer
There is everithing you need, you just have to look:
formatting link

Bye Jack
Reply to
jack4747
Use 7-Zip
formatting link
--
Dipl.-Inform(FH) Peter Heitzer, peter.heitzer@rz.uni-regensburg.de
Reply to
Peter Heitzer
No card there
Best I fpound was a 1725 page!!! pdf arm asm user guide.
--
If you tell a lie big enough and keep repeating it, people will  
eventually come to believe it. The lie can be maintained only for such  
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Reply to
The Natural Philosopher
On Wed, 18 Apr 2018 09:46:30 +0100 Gareth's Downstairs Computer wrote:
There's this *only* 112 pages long:
--
Steve O'Hara-Smith                          |   Directable Mirror Arrays 
C:\>WIN                                     | A better way to focus the sun 
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Reply to
Ahem A Rivet's Shot
Thanks, got that, no binary / octal / hex field information
Reply to
Gareth's Downstairs Computer

You are looking in the wrong place for simplicity.
?Reduced Instruction Set Computing? is an unfortunate misnomer, because it focuses on the instruction set, not the ?Reduced Complexity? of the hardware that implements it.
Virtually all reduced complexity machines have data manipulation instructions based on a register file with two read ports and one write port, thus supporting three-register instructions which can be executed in a single cycle. The data path includes an ALU and a barrel shifter, and the instruction encoding typically allows anything useful that can be done with them.
All data references are done with load and store instructions, permitting compilers to schedule longer latency instructions well ahead of references to the data values.
Since byte addressing is standard and data path width is 32- or 64-bits, it is extremely common to multiply addresses by small powers of 2, independent of the barrel shifter. Since only shifts of, say, 1 to 3 bits are common, these shifts are usually performed by a multiplexer on the side of the ALU which does not contain the complementer, thus balancing the delay of the complementer.
The result is relatively simple hardware which is capable of many simple operations in a single cycle instruction.
The simplicity of the data path is matched by the simplicity of the cache/memory interface, which allows only accesses aligned with natural data unit boundaries. This permits any memory transfer to be done in a single cache/memory access.
Of course, now all high performance machines dispatch multiple instructions per cycle and are almost universally MP-capable, so functional units and register file ports are multiplied and caches are much cleverer, but even these machines are much simpler than if they permitted, for example, unaligned word references (as other than an exception).
It would have been much less confusing if Berkeley had chosen Reduced Complexity Computer for the flagship implementation, but that?s history.
--
-michael - NadaNet 3.1 and AppleCrate II:  http://michaeljmahon.com
Reply to
Michael J. Mahon

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