Hopefully one last query

Computer ha scritto:

it's an ARM, so at

Bye Jack

Not so, for I have all the A53 manuals (one of them at 5000+ pages) but not the programmers card.

Thanks, I'll browse later when I've worked out how to "unzip" a tar file on windows.

There is everithing you need, you just have to look:

Bye Jack

Use 7-Zip

No card there

Best I fpound was a 1725 page!!! pdf arm asm user guide.

-- If you tell a lie big enough and keep repeating it, people will eventually come to believe it. The lie can be maintained only for such time as the State can shield the people from the political, economic and/or military consequences of the lie. It thus becomes vitally important for the State to use all of its powers to repress dissent, for the truth is the mortal enemy of the lie, and thus by extension, the truth is the greatest enemy of the State.

Joseph Goebbels

There's this *only* 112 pages long:

Thanks, got that, no binary / octal / hex field information

You are looking in the wrong place for simplicity.

?Reduced Instruction Set Computing? is an unfortunate misnomer, because it focuses on the instruction set, not the ?Reduced Complexity? of the hardware that implements it.

Virtually all reduced complexity machines have data manipulation instructions based on a register file with two read ports and one write port, thus supporting three-register instructions which can be executed in a single cycle. The data path includes an ALU and a barrel shifter, and the instruction encoding typically allows anything useful that can be done with them.

All data references are done with load and store instructions, permitting compilers to schedule longer latency instructions well ahead of references to the data values.

Since byte addressing is standard and data path width is 32- or 64-bits, it is extremely common to multiply addresses by small powers of 2, independent of the barrel shifter. Since only shifts of, say, 1 to 3 bits are common, these shifts are usually performed by a multiplexer on the side of the ALU which does not contain the complementer, thus balancing the delay of the complementer.

The result is relatively simple hardware which is capable of many simple operations in a single cycle instruction.

The simplicity of the data path is matched by the simplicity of the cache/memory interface, which allows only accesses aligned with natural data unit boundaries. This permits any memory transfer to be done in a single cache/memory access.

Of course, now all high performance machines dispatch multiple instructions per cycle and are almost universally MP-capable, so functional units and register file ports are multiplied and caches are much cleverer, but even these machines are much simpler than if they permitted, for example, unaligned word references (as other than an exception).

It would have been much less confusing if Berkeley had chosen Reduced Complexity Computer for the flagship implementation, but that?s history.