Forth

It's rare that you get to compare the same application, but we did get to convert a client's 68xxx app from direct-threaded to NCC (native code compiled). The difference in size for a 256 kb app was less than 2%, with the NCC version being smaller.

Stephen

So how does ARM handle peripheral hardware?

On INTEL you MUST have some assembler in a library at least to access I/O registers, because I/O is not part of Cs understanding of architecture..

Certainly that is so for I/O accessed by instructions that are separate from memory access, but not true where I/O is memory addressed, such as was on the PDP11.

This was part of the original C thinking where a number could be recast as something else ...

int *(65530), where my example of 65530 is intended as a memory based I/O address.

Welll that was what I said.

"So how does ARM handle peripheral hardware?"

I.e Does ARM have memory mapped IO?

Yes.

On Sun, 1 Jul 2018 12:06:17 +0100, The Natural Philosopher declaimed the following:

Something that should be easily found by perusing the documentation... EG: a lack of dedicated I/O port instructions, say... (since the ARM instruction set is probably the thinner document to study, and likely found on ARM's web-site).

The actual peripherals and memory map vary so much between implementations (remember, ARM sells designs for cores, but peripherals are manufacturer add-ons). TI's TIVA TMC4 series has entire "memory" banks whose only purpose is to set/clear single bits of memory ("bit-band" -- one bank for SRAM, one bank for "peripheral"). Instead of needing to load a word into a register, AND or OR a bit mask, and write the word back to memory -- one just accesses the "bit-band alias" address. A whole 32-MB of addresses just used to access single bits in a 1-MB region of real memory. One would need to study the implementation's documentation to determine the actual memory/peripheral addresses available.

I have seen C code like that handling memory mapped I/O - although the number was in hex.

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