Delayed thermal damage by lead-free soldering temperatures?

Any generic term for this/reasearch?

40 degree C/70 degree F, higher than traditional leaded solder temperatures, so otherwise like-for-like, more chance of excessive heat damage. Ignoring problems that emerge at component sampling/testing at manufacture (tin tinning of pins ) and post board soldering testing stage/ final product testing. What evidence is there for delayed damage effects, presumably probabalistically higher, due to the extra temperatures. What components would be more succeptible, ie presumably signal rather than power, SMD rather than traditional packages, 2 pin more so than multipin ?
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N_Cook
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temperatures,

product

Cannot find the relative frequency of thermal failure of active componentry at soldering stage , other than multilayer ceramic Cs , vias, plated-throughs problems seem to come out top in the overall failure stakes.

-- Diverse Devices, Southampton, England electronic hints and repair briefs , schematics/manuals list on

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Reply to
N_Cook

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