colilo help?

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to


I inherited an Arnewsh 5307 PROMO board. I identified some issues
with the monitor and upgraded dbug. dbug still does not correctly
init the ethernet chip but I am able to at least upload an srec image of
uClinux and execute it in ram.

Here's the problem. When I upload colilo using dbug

(colilo built CONFIG_FLASH, CONFIG_UI)

dl 80000
(places the image in ffe80000)

move jp1 from 1-2 to 2-3
(moves flash rom #2 to ffe00000)

hit reset button

colilo boots, I get the UI prompt. Everything works including gzip

Likewise if I have downloaded dbug using BDM and then, without power
cycling the board, overwrite with colilo + gziped uclinux image
everything works. I can unzip to memory and execute the image
everything works (except for the ethernet port, different issue
I'll fix it later).

When I power cycle the board (and colilo is in upper or lower
flash and jp1 is set appropriately) nothing works. The colilo
UI boot prompt does not show up etc.

Could someone please give me a hint? I am a reasonably good
coder but this is my first attempt at configuring a board
at bootstrap.

I've confirmed that the DIM is the one that was shipped
with the board. I've also got sufficient verified clean

Here is my board.c for colilo

void setupBoard()
        volatile unsigned char  *mbar;
        mbar = (volatile unsigned char *) MCF_MBAR;
        // CS0: Flash
        *((volatile unsigned short *) (mbar + MCFSIM_CSAR0)) = 0xffe0;
        *((volatile unsigned long *) (mbar + MCFSIM_CSMR0)) = 0x000f0001;
        *((volatile unsigned short *) (mbar + MCFSIM_CSCR0)) = 0x1980;
        *((volatile unsigned short *) (mbar + MCFSIM_CSBAR)) = 0x00000;
        *((volatile unsigned short *) (mbar + MCFSIM_CSBAMR)) = 0xFF00;

        // All of the CS defs prevent boot...
        /*CS1 */
        *((volatile unsigned short *) (mbar + MCFSIM_CSMR1)) = 0x0000;
        /* CS2: SRAM - Unpopulated on Arnewsh*/
        *((volatile unsigned short *) (mbar + MCFSIM_CSMR2)) = 0x0000;
        /*CS3 : Ethernet Controller*/
        *((volatile unsigned short *) (mbar + MCFSIM_CSMR3)) = 0x0000;
        /*CS4 - CS7*/
        *((volatile unsigned short *) (mbar + MCFSIM_CSMR4)) = 0x0000;
        *((volatile unsigned short *) (mbar + MCFSIM_CSMR5)) = 0x0000;
        *((volatile unsigned short *) (mbar + MCFSIM_CSMR6)) = 0x0000;
        *((volatile unsigned short *) (mbar + MCFSIM_CSMR7)) = 0x0000;

void setupDRAM()
// From the setup file gotten from moto

        volatile unsigned char *mbar = (unsigned char *)MCF_MBAR;
        unsigned long   junk = 0xA5A59696;
        // everything here is based on having the original sm564013074n6aa
        // SMART DIM installed. This is 8 Mb of ram
        //;DCR: SDRAM  
        // SO = 1 - Synchronous Operation
        // NAM = 0 - CTLR Muxs Ext Addr Buss to provide Col Addr
        // COC = 0 - SCKE is CLK EN, Self Refresh via DRAM CTLR
        // IS = 0 - Take no action on Self Refresh * May need to change this
        // RTIM = 01 - Number of clocks inserted between a REF and an ACTV
        // - Refresh Timing
        // RC = A - The number of buss clocks between refresh cycles is
        // (RC+1)*16 = 176
        *((volatile unsigned short *) (mbar + MCFSIM_DCR)) = 0x822A;
        //;DACR0: base=0x00000000; timing=2,4,2,1,-1; CBM01%1
        *((volatile unsigned long *) (mbar + MCFSIM_DACR0)) = 0x00001304;
        //;DCMR0: mask=4MB; enable
        *((volatile unsigned long *) (mbar + MCFSIM_DMR0)) = 0x003c0001;
        //;DACR1: base=0x00400000; timing=2,4,2,1,-1; CBM01%1
        *((volatile unsigned long *) (mbar + MCFSIM_DACR1)) = 0x00401304;
        //;DCMR1: mask=4MB; enable;
        *((volatile unsigned long *) (mbar + MCFSIM_DMR1)) = 0x003c0001;
        //;DACR0: Initiate Precharge All Command
        *((volatile unsigned long *) (mbar + MCFSIM_DACR0)) = 0x0000130C;
        //;DACR1: Initiate Precharge All Command
        *((volatile unsigned long *) (mbar + MCFSIM_DACR1)) = 0x0040130C;
        //;Execute PALL command - a write to any address performs the precharge
        *((volatile unsigned long *) 0x00000000) = junk;
        // Remember that there are two banks of SDRAM
        //;Execute PALL command - a write to any address performs the precharge
        *((volatile unsigned long *) 0x00400000) = junk;
        //;DACR0: enable refresh
        *((volatile unsigned long *) (mbar + MCFSIM_DACR0)) = 0x00009304;
        //;DACR1: enable refresh
        *((volatile unsigned long *) (mbar + MCFSIM_DACR1)) = 0x00409304;
        //;Delay for Refresh
        //;DACR0: Initiate Mode Register Set Command
        *((volatile unsigned long *) (mbar + MCFSIM_DACR0)) = 0x00009344;
        //;DACR1: Initiate Mode Register Set Command
        *((volatile unsigned long *) (mbar + MCFSIM_DACR1)) = 0x00409344;
        //;Execute MRS command
        *((volatile unsigned long *) 0x400) = junk;

        //;Execute MRS command
        *((volatile unsigned long *) 0x400400) = junk;


        flash   : ORIGIN = 0xffe00000, LENGTH = 0x00005000
        ram     : ORIGIN = 0x07BFFFF, LENGTH = 0x0040000

Thanks in advance.


Site Timeline