Hi group
In order to keep traces as short as possible I would like to route the PHY's MII interface to the built in EMAC0 with as short traces as possible. Xilinx consequently recommends to use IOs which are close to the EMAC. However, I could not find documentation (I'm aparently overlooking it) close to which bank the EMAC is located..... So does anyone know and tell me? While we are at it, where's the PPC core?
This is for a Virtex 4 FX 12 btw.
TIA
Markus
You can use the FPGA editor that is part of ISE to look at where the EMAC and PPC are located with respect to the pins/pads for the package that you are using.
Regards,
John McCaskill
John,
Just to be on the save side, and sorry if this is a dumb question, but with "FPGA editor" you mean the "Pinout and Area Constraints Editor (PACE)" ?
If not, where do I find the FPGA editor, or better said, how do I invoke it?
TIA
Markus
No, I did not mean the PACE tool, but I think it might show you what you want to know. I have not used PACE in quite a while now. I am working in EDK so I generate area group constraints with TCL scripts that are part of my core designs.
On a Windows computer, the FPGA editor is at:
Start->All Programs->Xilinx ISE 8.2i->Accessories->FPGA Editor
This should be the same menu that has the PACE tool in it.
I am not sure, but I do not think that the FPGA Editor is not part of the Web Pack version of the tools if that is what you are using. I have the ISE Foundation version.
Regards,
John McCaskill
FPGA Editor is part of the Web Pack version and I found it. Thanks for the pointer.
Markus
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