Tracking down HardWired History

Yielded a wealth of information.

We had three different versions of hardwire (to my recollection): the first was simple via (?) layer to connect memory cells to 1's and 0's which had no area advantage over a regular FPGA, the second was a relayout with less area still programmed by a single layer, and the last version was more like a standard cell ASIC flow.

All had incredible problems, as they were no different than an ASIC! If a mistake was made by the customer, it had to be changed, and fab'd again. If the timing was different (which it always was), the customer would either have to make changes, or the part would have to get changed yet once again. Since the hardwire parts ran in separate wafer lots, they had all the problems of ASICs: process variation, lot to lot differences, infrequent fab cycles, poor yield, etc. etc. etc.

That is why EasyPath(tm) is sooo attractive to us. Been there, done that.

There is a real obvious reason why we abandoned HardWire: it led nowhere. The total Structured ASIC business (the new fancy name for this business) was about 68 million US$ in 2003 (from a survey). It is estimated to be about 900 million US$ by 2007 (from the same survey). I don't believe these numbers at all (I think they are too large). Financial folks have also passed the business by as a "non-starter."

Split among 10+ competitors, it is a pretty uninteresting business model to go after, especially since looks like 10+ tom cats fighting over one mouse .... one mouse at a time!

I get much more excited about things like:

Austin

Bill Cox wrote:

In the light of recent comments on this site relating to Structured-ASICs in general and Altera and HardCopy in particular, I would like to correct a few factual inaccuracies which may have crept in.

Our competition is apparently basing its decision not to follow our lead into this market on its experience with a failed product from years gone by. I would say two things about this. Firstly, technology has moved on. In the 1990s, it was not possible to base the heart of a complex system on an FPGA - they were too small. This has obviously changed, such that a single FPGA can now cover over 80% of all ASIC starts. Secondly, the increasing costs of ASIC NREs now represent a considerable barrier to the use of ASICs - this was not the case in the '90s, as NREs were typically less than $200K at that point. Deciding not to do a Structured-ASIC product today on the basis of experience from 10 years ago is a bit like a camera company deciding not to produce a digital camera today because they tried it when resolution was 300K pixels and nobody bought them! The financial community is certainly not of the opinion that this is a "non-starter".

We have now completed over 50 HardCopy tapeouts and are running at a rate of over 1 per week. We believe that this means that HardCopy is currently leading the Structured-ASIC market in terms of tapeouts. The rate of designs being booked is increasing, and our backlog indicates that 2005 will see revenue tripling based on the designs that were booked in 2004. The current version of HardCopy has been shipping for exactly one year now, and its combination of seamless, risk-free migration together with the ability to reduce power and increase performance over the FPGA is unique in the industry. Clearly the Structured-ASIC industry is new and relatively small at present. However, like many of the significant players in the ASIC market, Altera believes that it will grow strongly over the next few years, and our design bookings confirm this. We are very happy to be alone in this market.

Paul Hollingworth Altera Marketing

Paul,

Wow. 50 hardcopies. In a whole year (or two). Thanks for admitting the "non-starter" status of this. (We get > 50 design-ins per month with our FPGA's).

And, "seamless risk free" is just a plain an outright misrepresentation.

I know of a customer that had a serious issue, and was unable to meet their production ship dates (fact). Only reason we know is that they had to continue buying the FPGA (ours).

Have fun in this business! Good luck! One less competitor for real FPGAs.

Austin

Paul Holl> In the light of recent comments on this site relating to

"Austin Lesea" wrote

Without taking sides on the underlying debate, is there a possibility that problems and design practices masked by the slower FPGA speeds come and bite at ASIC speed?

Not everyone has read and followed the stuff on crossing clock domains and so on.

I'm just wondering how come fully debugged (!) designs can go all bad.

Tim,

The case at issue was one where the hardened version was much faster. The much faster part was the IO itself was now much faster, and had less delay (a real issue when you are cutting out real estate to get the cost advantages - things get faster - it is unavoidable).

So, speed (too slow) was not an issue. Speed (way too fast) was an issue. If the other part this one talked to was a FPGA, no problem, just reprogram the FPGA to accept that the signals were arriving a little ahead of where they used to.

Too bad, they had already made that part an ASIC (from an ASIC vendor) just a few months earlier.

Result, throw away all of the hardened parts, and go back to using the FPGA. Oh, and stick the vendor with the cost of failure as it was "guaranteed." It could be that this is what Paul is referring to: no cost of failure, as it will be paid for by the vendor until they get it right. Not my idea of a great business model, but hey, I don't like the whole hardened model anyway.

Bottom line:

If it ain't broke, don't fix it. An engineering maxim that was true years ago, and still true today. Change anything, and something will change (obvious, isn't it?).

Will it be the IO timing? The IO signal integrity? The jitter performance? Will it be too fast? Will it be too slow (unlikely)?

DOH!

The ONLY solution that can make the claim of no pain, is ours: EASYPATH(tm). Why?

Because we don't change anything at all. Same part, same silicon, same bitstream, just 30 to 50% (or more) cost savings.

How could any person examining the costs of a product ignore EasyPath? Once the accounting folks (and CEO) understand the lack of risk, and the reduction in costs, an engineer's opinion (of goodness of badness) will not be worth a cent. The facts speak for themselves.

Austin

Tim wrote:

Hi, Austin.

Thank you for your description of the three families. This confirms what I've heard before. I've checked out about the first 200 links yielded by Google when searching for 'xilinx hardwire'. Every one is about the most recent gate-array based family. The first two families seem to be hard to track down.

My patent laywer is asking me for public documents on the first two families, since these are considered strong prior art in the structured ASIC market. Unfortunately, these families were gone before the web took off, so there was never any on-line docs, so Google hasn't helped me. Of course, the devices themselves can still be found, and that's technically enough.

Thanks, Bill

Bill,

Why didn't you say you were looking for prior art?

Consult uspto.gov and do a search for xilinx, hardwire, etc.

I am sure our IP lehal folks filed something!

Best of luck with your endeavour (invention).

If there is something you wish to discuss with Xilinx, I am gappy to direct you to th4e right folks,

Austin

Aust> Hi, Austin.

Hi, Austin.

IMO, the most important patent Xilinx filed in the field is 5068603. It covers tons.

However, I still need more info on the HardWire 1 and 2 families.

Thanks, Bill

aust> Bill,

confirms

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families

structured

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helped

that's

bill,

email me at snipped-for-privacy@xilinx.com directly to discuss,

aust> Hi, Austin.