Re: Q: regarding I2C protocols

So the question I have for those who have really done this is -

>in the real world, could a master (or series of masters) issue >a STOP command followed by a START command - all on the same >SCL high period. The latest I2C spec doesn't explain whether >or not this could happen.

Anything can happen. Please consider combinations of fast CPUs and sudden power-loss or reset in _all_ phases of the protocol. Remember for example the "I2C Edge Conditions" problem.

Wolfgang Denk

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Wolfgang Denk
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