jBits RouteClock

Hello, Is there anyone who has successfully applied com.xilinx.util.RouteClock?

I applied RouteClock to a full bitstream as you suggested. But unfortunately this seemed to have some side-effect, which led to malfunctioning of the bitstream. I programmed a tool which re-translated the bitstreams to the commands described in xilinx's virtex-II user guide and encountered some differences. I hope you can help me find the reason for the malfunctioning:

  1. before: ...
3000C001 MASK Masking Register for CTL 00000008 MASK Register value 30008001 CMD Write to Command Register 00000009 SWITCH Switch CCLK Frequency 30002001 FAR Frame Address Register 00000000 Frame Address 30008001 CMD Write to Command Register 00000001 WCFG Write Config Data 30004000 FDRI followed by Type 2 Packet Header 5004926E TYPE2 Word Count = 299630 00000000 Data Word 1 00000000 Data Word 2 ...

after RouteClock: CTL register write moved down to the end of the bitstream, CMD SWITCH vanished, the FDRI command seems to have changed to "04804000" - what's the meaning of that command?: ...

3000C001 MASK Masking Register for CTL 00000008 MASK Register value 3000A001 CTL Control Register 00000008 Control Register value 30002001 FAR Frame Address Register 00000000 Frame Address 30008001 CMD Write to Command Register 00000001 WCFG Write Config Data 04804000 5004926E 00120480 00000000 00000000 ...

  1. before: (config data)...

00000000 Data Word 299629 00000000 Data Word 299630 0000DEFC 30008001 CMD Write to Command Register 0000000A GRESTORE Pulse GRESTORE Signal 30008001 CMD Write to Command Register 00000003 DGHIGH De-asserts GHIGH 20000000 20000000 ...

after RouteClock: CMD GRESTORE moved to the end, some FAR FDRI (data) commands are added - I guess there lies the clock net routing information: (config data)...

00000000 00000000 0000DEFC 30008001 CMD Write to Command Register 00000003 DGHIGH De-asserts GHIGH 20000000 20000000

  1. before: ...

20000000 20000000 30008001 CMD Write to Command Register 00000005 START Begin STARTUP Sequence 3000A001 CTL Control Register 00000008 Control Register value 30000001 CRC CRC Register 0000DEFC CRC Register value 30008001 CMD Write to Command Register 0000000D DESYNCH Forces Realignment to 32 bits 20000000 20000000 20000000 20000000 (end of bitstream)

after RouteClock: GRESTORE is now located here, while the CTL command setting the "persist" flag is at the beginning of the bitstream... ...

00000000 Data Word 497 00000000 Data Word 498 0000DEFC 30008001 CMD Write to Command Register 0000000A GRESTORE Pulse GRESTORE Signal 30008001 CMD Write to Command Register 00000005 START Begin STARTUP Sequence 30000001 CRC CRC Register 0000DEFC CRC Register value 30008001 CMD Write to Command Register 0000000D DESYNCH Forces Realignment to 32 bits 20000000 20000000 20000000 20000000 (end of bitstream)

Well, i hope i didn't provide too much unnecessary information. If someone needs more information to be able to help please post a reply.

Thanks in advance for your support Simon

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simon
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