Hello everybody,
I am trying to gain a deeper understanding of the way an FPGA is programmed.
For SRAM based FPGAs, I know the configuration is loaded either by row, column or frame.
But how exactaly are the SRAM cells programmed?
Are they part of a long shift register, which is filled in by the configuration bitstream?
Or is there something I am missing?
If there is any paper or article describing this, I'd be glad if anyone could point it out to me.
I realize that, for manufacturers, this might be proprietry information, but surely there's some work out there describing the process?
Thank you very much for your help.