Any processors with a decent trace bit/single step support should be able to handle this quite easily, although not in real time :-).
In such systems, the trace interrupt service routine is executed after each instruction, so it is easy to create a trace buffer. For instance on the PDP-11, the trace mode used the same ISR as the breakpoint trap ISR, so you had to check from the processor status word, if the T (trace) bit was set or not, to determine, what was the cause of the interrupt.
On processors that does not support the trace/single step feature, it would be a good idea to check what happens if an interrupt line is constantly active, does it execute the same ISR again without executing even a single instruction or does it execute the next instruction and then executes the ISR again. In the latter case, this feature could be used to build the trace buffer.
Even with edge sensitive interrupts, the trace feature could be implemented with a minimum hardware (a simple monostable). The trace ISR triggers the monostable and the monostable output is connected to the interrupt request pin. The falling edge of the monostable activates the interrupt again. Instead of a monostable, a few inverters in series could produce enough delay so that the ISR exits and the decoding of the next instruction will advance to a point that the next instruction is executed, even if the interrupt request line is active.
Paul