On most (all?) CPUs the locations for non-maskable interrupt vectors are fixed in the hardware. The other (maskable) interrupts may also be in fixed locations (common on 8-bit chips) or may be in a relocatable table.
It _always_ helps, when asking about a processor, to tell us what specific processor you're using. Just saying it's an 8051 or an ARM isn't enough
-- give us a part number. We can either go from there, or decide that we're too lazy to try.
As mentioned, some processors allow you to relocate the interrupt vector table. This is usually done by allowing you to set the interrupt vector table starting location in a register, although sometimes you just get to put it into one of two places with a flag, or some other limited scheme.
I found the documentation for INTB. It indicates the start address of an interrupt vector table. I think this is the start address of fixed interrupt vector table located at 0xFFFDC to 0xFFFFF.
Besides this fixed vector table, how many other vector tables does this Renesas M16C / 6N5 Group Microcontroller have ? If it has a relocatable vector table, how does it work ? What is it used for ? Why does it need to be relocatable ?
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I think you're getting your definitions confused. I very much suspect (and a close reading of the data sheet should reveal) that the processor only has one interrupt vector table at any one time. If you specify the location of the interrupt table in a register, then the interrupt table location is, ipso facto, not fixed.
Perhaps a better term (if I'm correct) would be to call the 0xfffdc location to be the _default_ interrupt vector table location.
Depending on how you define things, always one (because the register only points to one place at a time), or as many as the system programmer thinks is appropriate.
Your questions, in reverse order:
You may want a relocatable interrupt vector table because you may want to locate it in RAM, to give you the flexibility of assigning interrupt vectors dynamically.
Many real-time operating systems have a facility that lets the application programmer set the location of an interrupt vector with an appropriate call. This can only be done if the interrupt vector table is in RAM.
It's also a useful thing if you have two sets of code that run on the same processor. I'll often have a separate boot code block that comes up by default, checks the application code for validity, then jumps to application code. In the ARM Cortex parts that I'm currently using, the application code will have its own interrupt vector table at a different location from the boot code's. While all of the interrupt vectors are hard-coded and thus known to the application code at link time, they won't be known to the boot code -- having a location for the app code's interrupt vector table vastly simplifies making the switch from boot to app code.
At some time, preferably before any interrupts have been turned on, the start-up code will change the location of the interrupt vector table to wherever the system programmer needs it. Subsequent software will then know where it is, and respond appropriately.
Looking at the hardware manual for this processor (much more detail than the datasheet), there are TWO different interrupt vector tables. One, the fixed vector table is always at a fixed location, and it primarily handles exceptions and traps (UND instruction, Overflow, BRK, NMI and the like), and a separate relocatable vector which has its located based on INTB to handle things like device interrupts and the INT instructions.
It looks like the idea is that in ROM you have a basic system with debugger, with its needed vectors in ROM, but the user program can move the interrupts not needed for debugging for its own use.