Serial CPLD

I've been using shell (Xilinx) and tcl (Altera) scripts and makefiles for FPGA builds. For a Xilinx flow you will typically run:

partgen -p $(PART) xst -ifn xst.cmd ngdbuild -uc ../$(CHIP).ucf -p $(PART) map -p $(PART) -pr b -detail $(CHIP) par -w -ol high $< $@ $(CHIP).pcf trce -skew -a -v 1000 $< $(CHIP).pcf netgen -sim -aka -dir . -ofmt verilog -pcf $(CHIP).pcf -sdf_anno true

-sdf_path ../../impl/2vp100/xst-compiled -w $< $@ bitgen -w -g DCIUpdateMode:quiet -g ConfigRate:15 -g Compress $< $@ promgen -c -w -p mcs -x xcf32p -u 0 $< impact -batch program-prom-svf.imp

BTW I've never used the Web version of ISE. Don't know if all of the above is available in the Web edition.

Well, these days you're better off with VHDL or (System)Verilog...

Petter

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Petter Gustad
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So I was wrong thinking that. I had only looked at the tools, never used them - I have used the original (Philips) Coolrunner with a tool I have written. I have some data on the new ones and I will see how much I can guess what I do not have to decide how practical it will be to try to adapt my tools to the coolrunner 2, but this is still TBD.

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Reply to
Didi

The SPI port would run at some MHz, so interface delays should be the same as a parallel SW strobe one, and certainly minimal relative to the Comms speeds. SPI is really a pin-saver, and the SPI one allows multiple-bytes to be sent, plus it is a peripheral already bolted onto the core.

CPLD Low power candidates: Atmel ATF150x family 32/64MC at 44 pins, Good logic packing. Also low power BE family. Above 64MC (macrocell) and you are at 100 pins. Nice simple tool flows.

Xilinx Coolrunner families: Multiple Vcc's, but low power, and good package choice.

Lattice Mach4000Z: Similar to the above. Again, over 64MC and you are at 100 pins.

How many macrocells depends on what happens where. You might be able to move the Txmit CRC into the ARM, and maybe RX CRC, so 64MC is a target to consider.

How long is the packet, and appx content ? Arbitration is by ?

-jg

Reply to
Jim Granville

Atmel's WinCUPL can certainly do that (very similar to Abel). We have set it up to run under a Std Text editor (NP++, or PSPad), and command line everything, then the tool is almost invisible, except for the brief 1-2 second flash when it compiles/simulates/fits. I have not tried WinCUPL under Linux, but the command line engine is very lowest-common-denominator stuff DOS level screen IO.

-jg

Reply to
Jim Granville

Nope. Windows version.

Mark

Reply to
Mark Borgerson

There is also a protocol that must be implemented between the man and peripheral micro over the SPI bus. This protocol must at *least*: multiplex control and data; define the various control, status and types; frame the transactions; provide binary transparency; all of which add additional complexity and constraints to the system software. Yes, it can be done... yes, I've done it before, but I'd rather not ;-) Especially on the resource constrained MCU side.

Thank you for that summary Jim.

I'll give that some thought.

Varies, but no more than 64 bytes.

The synchronous bus takes advantage of the "dominant" bit feature to detect collisions on a bit-by-bit basis without causing a retransmission. Dominant bit bit transmitter wins. The bit patterns of the first portion of the packet contain packet priority information followed by "MAC" address style information.

Again, thanks for the advice/info.

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Reply to
Michael N. Moran

CUPL has been around for a while, but I never used it. How good is CUPL's state-machine description language compared to say ... ABEL? :-) Not that I'm resistant to change ;-)

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Michael N. Moran

-sdf_path ../../impl/2vp100/xst-compiled -w $< $@

There is hope! :-)

I looked at VHDL when in its infancy. My approach was to read the existing specs, but I got rather lost. Do you have any recommendations/pointers for online introductions, tutorials, references or dead-tree literature?

Thanks peter.

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Reply to
Michael N. Moran

I like Skahill _VHDL For Programmable Logic_. Out of print, but available used for $10-$15.

Best regards, Spehro Pefhany

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Reply to
Spehro Pefhany

This is a snippet from a CUPL file: pretty simple Present / next code. This one is a reverse Bit-Stuffer, that finds a sync pulse in a defined data stream.

SequenceD Sync{ present 'd'0 if SPI_DI next 'd'1; default next 'd'0; present 'd'1 if SPI_DI next 'd'2; default next 'd'0; present 'd'2 if SPI_DI next 'd'3; default next 'd'0; present 'd'3 if SPI_DI next 'd'4; default next 'd'0; present 'd'4 if SPI_DI next 'd'0; if SPI_DI OUT SyncH5; default next 'd'0; present 'd'5 default next 'd'0; /* these provide safe covereage */ present 'd'6 default next 'd'0; present 'd'7 default next 'd'0; } MIN Sync.d = 2; /* logic Minimize */

CUPL includes a simple functional simulator, so you can test these easily.

Reply to
Jim Granville

Yes and no. With the SPI running much faster than the final bus, its use is not too different to a parallel bus. If you send 16 bit transactions, you have a byte, and 8 control bits, and can get back DUPLEX info, from the slave.

So that's above what you can store (practically) in a CPLD, but still within small uC abilities. 64bytes is big in CPLD terms, but OK in bottm-end FPGA terms.

The CPLD can easily do the bit stuff, and bit level arbitrate, and flag any loss.

Given what you have described a hybrid design could be a candidate : configure the ARM SPI as slave, and use a few parallel pin for Arbitrate loss, and START found, The CPLD then clocks data in/out of the SPI as it needs to and will skip SPI clocks during bit-stuff. viz : The SPI is a serial FIFO, and the CPLD does the bit-massage (where it excells), but no data storage (where it is not efficent).

If the packet data is sub-packet interactive, where the first NN bits determine what goes in YY later bits, in the SAME packet, then things get a lot tougher.

Would need some quick tests of the SPI slave mode on your target ARM.

-jg

Reply to
Jim Granville

It's been quite some time since I learned Verilog (from the Gateway manual after been using HILO) and VHDL so I'm probably not the best to ask. I suggest you read the FAQ and/or post your question in comp.lang.verilog and comp.lang.vhdl.

I think Xilinx had a tool which could convert ABEL to VHDL, can't remember the name...

Petter

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Reply to
Petter Gustad

Yep; I use the altera quartus web edition using the command line and a custom Makefile.

Cheers, mvdw

Reply to
Matt van de Werken

I had not planned on storing the packet on the CPLD. I'm thinking stream the data as it comes in and at the end-of-frame get a CRC indication and decide to discard or not. In the mean-time, the CPLD would do the error signaling on the bus.

This hybrid design is essentially what I am considering, but using a parallel interface rather than the SPI. It seems to me that given the number of macro-cells that I'll need for the serial bus logic, having the extra (16 or so) I/O pins for the 8-bit bus interface won't be a problem. Most of the ARM SOC's that I've seen have plenty of chip-select controller logic built-in to make gluing the CPLD to the bus pretty straight forward. The benefit is that the resulting driver on the ARM would be more straight forward.

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Reply to
Michael N. Moran

Xilinx have examples for coolrunner in both Verilog and VHDL..

Regards Anton Erasmus

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Reply to
Anton Erasmus

-sdf_path ../../impl/2vp100/xst-compiled -w $< $@

I bought one of the Xilinx development kits, and used the Web Edition of their tools. All the examples that came with the kit used a batch file to run all the tools. So using the Web Edition from command line is not a problem.

Regards Anton Erasmus

Reply to
Anton Erasmus

The name is xport. It can convert ABEL or AHDL to either Verilog or VHDL.

Regards Anton Erasmus

Reply to
Anton Erasmus

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