I've been using shell (Xilinx) and tcl (Altera) scripts and makefiles for FPGA builds. For a Xilinx flow you will typically run:
partgen -p $(PART) xst -ifn xst.cmd ngdbuild -uc ../$(CHIP).ucf -p $(PART) map -p $(PART) -pr b -detail $(CHIP) par -w -ol high $< $@ $(CHIP).pcf trce -skew -a -v 1000 $< $(CHIP).pcf netgen -sim -aka -dir . -ofmt verilog -pcf $(CHIP).pcf -sdf_anno true
-sdf_path ../../impl/2vp100/xst-compiled -w $< $@ bitgen -w -g DCIUpdateMode:quiet -g ConfigRate:15 -g Compress $< $@ promgen -c -w -p mcs -x xcf32p -u 0 $< impact -batch program-prom-svf.imp
BTW I've never used the Web version of ISE. Don't know if all of the above is available in the Web edition.
Well, these days you're better off with VHDL or (System)Verilog...
Petter