Hello, Who knows if the transceiver is really on-chip or if it is a two chip solution in one housing?
Heinz
Hello, Who knows if the transceiver is really on-chip or if it is a two chip solution in one housing?
Heinz
I recall reading in a NXP release it was a 2 die solution ?
--jg
What about x-raying or grinding down the housing?
-- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
Or crack one open with a pair of heavy duty wire cutters ?
I better trust the knowledge of people in this gropu insteda of using brute force methods.
Heinz
Op Tue, 13 Dec 2011 23:38:38 +0100 schreef Heinz-J=FCrgen Oertel =
:ip
=
No knowledge in this group, just anecdotes and speculation.
-- Gemaakt met Opera's revolutionaire e-mailprogramma: = http://www.opera.com/mail/
1) How do you think people in this group are going to find out? 2) If you open one up and see one or two chips, you _know_ the answer. What reason have you got to trust some random person on Usenet?
-- Grant Edwards grant.b.edwards Yow! NEWARK has been at REZONED!! DES MOINES has
rute=20
Who cares. Even if you know if there is one or two chips in a package,=20 how would it change anything.
VLV
Is the chip very expensive? If not, it's a real on-chip solution - dual die packaging normally costs a lot more.
Just out of curiosity - why do you care? What difference does it make to your use of the chip? Either the chip meets your price/packaging/performance/functionality requirements or it doesn't. I can't see how knowing what is inside changes that. Or is it just for curiosity?
Regards, Richard.
Yes Heinz
I _know_ some are working for or closely with NXP.
Because I read articles in c.a.e. since years. I would trust persons who are regularily posting here meaningful content.
Regards Heinz
The price increment is about the same as a separate transceiver. I always assumed it was on-chip, but this post has made me think again. The description does say "includes a TJF1051/3 transceiver".
I am now inclined to take that literally!
-- John Devereux
As far as I understand dual-die chip making (and that's not /very/ far, so I could be wrong) it's generally more expensive than making two separate chips, unless the package is a particularly expensive type. As well as testing each die in advance, you've got a special mounting process with a different kind of connection between the dies. A company like NXP will produce vast quantities of single-die devices in their standard packages - the process is very automated, and therefore cheap. That's why some packages are cheap than others, even if they are bigger and have more pins - if the package and the machines that make them are more popular, the process is cheaper.
So I would be inclined to take your price information as an indication that it is a single die device - but of course I can't be conclusive.
Compare the Xilinx XC3S50AN versus the XC3S50A. It must be a two chip solution, to all what I can judge about Xilinx contract manufacturing.
Also the XC3S50AN is a little more expensive than the a XC3S50A plus serial flash, it dosen't "cost a lot more.
-- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
Yes we are all speculating.
In that vein, TJA1051 can withstand continuous +/-58V on it's CAN lines. And 8kV ESD. Is that really possible on a 50MHz ARM?
Suggestive diagram on P54 of the datasheet.
-- John Devereux
Check Vesd on page 28.
haha yes looks like the 6 "external" TJA1051 pins have their own, different, separately specified ratings. It really does look like it's a separate chip.
-- John Devereux
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