Whilst trying to track down an obscure bug, I noticed that ST header files do not specify volatile for peripheral registers. In contrast ARM stuff (looking at CMSIS) is religious about volatile.
For example, in stm32f413xx.h there's lots of stuff like #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) // nice hex address #define TIM2 ((TIM_TypeDef *) TIM2_BASE) // TIM2-> used throughout
No volatile on the pointer declaration (nor structures wouldn't work for typedef?)
I checked some headers from Freescale/NXP (OK, a few years old), same thing.
Am I missing something, or is this omission completely nuts? A lot of register access will be intolerant of 'optimization', right? David B. ?
Thanks in advance, Best Regards, Dave