low-power, high capacity data queue design ideas

Why are you looking at complicated FPGA solutions when what you are asking about could easily be done by, say, an MSP430 microcontroller in a few milliamps? The main power cost in this case being the SD writes, which should be buffered in RAM as far as possible (certainly for 512 bytes at a minimum). Leave the CPU sleeping until it gets the data received interrupt, to save a bit more power.

You don't want to get into USB if you can possibly avoid it, plus USB will require 5V supply in your system and generally a linear regulator in the memory stick wasting power to bring the 5V back down to 3.3V or

How expensive are SD writes in terms of energy?

I don't have the data to hand, but I have done this analysis for 1 month's operation for 48Kbytes/hr being written vs. buffering to a

How critical is reliability vs power consumption? If you have no non-volatile memory, and just keep everything in a horrific amount of SDRAM, and the widget loses power and the data vanishes into the void, is that a mild inconvenience or does it bomb the wrong embassy?

--=20 Rob Gaddi, Highland Technology Email address is currently out of order

You ask this question in a manner that implies the two ideas are mutually exclusive. But good point.

You ask this question in a manner that implies the two ideas are mutually exclusive. But good point.

I don't have the full design details, but I am guessing that it's a mild inconvenience.

To be honest, I haven't done the FPGA vs. Microcontroller power comparison.

I do FPGAs and a group has come to me and said that they've determined that an FPGA was the way to go. I don't know how they made that determination.

But... I think part of their rationale is that this thing is never going to be in a sleep state as the incoming data is constantly coming in... and to achieve the 8MBps rate out (along with overhead) they'd have to clock the microcontroller relatively fast. I think they had a PIC in mind when they were making these decisions.