Thanks for the information. I must say I'm impressed with your design
- a great interoperability of logic, cores, small and large CPUs and software.
Eli
Thanks for the information. I must say I'm impressed with your design
- a great interoperability of logic, cores, small and large CPUs and software.
Eli
(snip)
You could, but sending UDP isn't that much harder. If you really want to simplify it, put the destination MAC address in as a constant (saves doing ARP, but ARP could also be done in external software and the result written to the FPGA). The next complication is generating the CRC for UDP, but that is optional. The ethernet CRC has to be generated in either case.
(snip)
If the FPGA isn't fast enough, write it out in 8 bit parallel and use an external shift register.
-- glen
There are a number of things that can be used to speed up the Ethernet communication (I've read about these, but not tried them - but they might give you a clue).
On the software side, there are a number of different tcp/ip stacks available, and the particular implementation can make a lot of difference.
In the FPGA, you can make sure you are using DMA for memory transfers rather than cpu memory accesses. You can also use the FPGA to accelerate things like CRC calculations enormously - perhaps you can get these ready-written, or make one yourself, and modify the stack to use it.
There are also several different Ethernet MAC's available, with widely different throughputs. Have a look at the OpenCores lists and try some out (I gather the prices are not insignificant, but they may be worth the money).
mvh.,
David
This is exactly why direct MAC communication is undesirable here. Tying the sender to the receiver's MAC address as a constant isn't good engineering.
Indeed. ARP needs to be done only once in a while anyway, so it can be done by a slow software program.
CRC generation in FPGAs is blazing fast, so I don't really see a problem here.
Eli
Thanks for the compliment!
I really like the PicoBlaze. It makes a great compliment to the PowerPC, and is very small. It is very good in this appication of being an IO processor.
Regards,
John McCaskill
I think you are missing the big picture.
Before you can do ARP, you have to have an IP Address. Where did that come from? Why not provide the MAC address through the same path?
If you have a send-only application, you don't need any protocol stack. Just fill in a few constants and blast away.
Yes, it might be convenient to have some software around.
-- These are my opinions, not necessarily my employer's. I hate spam.
The next complication is
UDP doesn't have a CRC. There is a software checksum, but it's designed to be easy to compute with typical CPUs. There is a clean way to say "none".
Just for the record...
The Ethernet CRC is not really necessary. It's getting kludgy to avoid it, but it can be done. The trick is to get the adapter on the receive side to give you the bad packet too. That may be hard/impossible on some of them. I haven't tried to do it in ages. It used to be a common hack for debugging.
-- These are my opinions, not necessarily my employer's. I hate spam.
The IP address can be statically allocated. If my recipient changes the computer during the runtime of the system (years), his MAC changes, but not his IP.
Eli
You could quite safely use some random private IP address, such as
192.168.123.45 as the target address and require the receiver to specify this IP address on one of the their Ethernet adaptors. You just need to do the ARP translation to get the MAC address.If the target PC is swapped, you just have to redo the ARP translation at startup. This is quite sufficient in any non-redundant system.
Paul
The IP address can be static to the FPGA, in a programmable register written into be an external processor doing ARP.
You can also use BOOTP to load the hosts own IP address, with the destination IP address as one of the BOOTP options. That can all be done in an external processor (or processor internal to the FPGA).
-- glen
Hi Eli,
I am build a similar thing: a GLAN high-speed camera based on low-cost Avnet Virtex4 Mini-Module. I modified Xilinx GSRD2 to fit on this module. Sending pure ethernet frames you can achieve 730-850 MBit/s. The LL_TEMAC is DMA based peripheral with hardware checksum. If you need any other information or the complete desing do not hesitate to contact me.
Chers,
Guru
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