Extended life of EEPROM counter? - Page 2

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
Re: EEPROM endurance question
Hello Robert,

Take a look at Microchip's application notes AN537 (and AN536 and AN
602). They give you a bright idea about what endurance is and how to get
most out of your EEPROM.


Robert Scott wrote:
Quoted text here. Click to load it

Re: EEPROM counter endurance
On Fri, 08 Aug 2003 08:55:24 +0200, Aart van Beuzekom

Quoted text here. Click to load it

Good suggestion.  I found this in AN537:

  "Indeed, this write all 0s test pattern
   will produce very different results than a
   checkerboard test pattern of alternating 1s
   and 0s within a byte, since cells are
   changed more often writing all 0s than in
   an alternating 1 and 0 write pattern."

This seems to confirm that not all writes are equal, and that there
may some value to implementing a counter where the transitions from
"0" to "1" are delayed as long as possible so as to minimize the
number of bit changes.

-Robert Scott
 Ypsilanti, Michigan
(Reply through newsgroups, not by direct e-mail, as automatic reply address is

Re: Extended life of EEPROM counter?

Quoted text here. Click to load it

I was thinking along the same lines, but how about the shift register
clearing only a bit at a time as well:

00-01-03-07-0F-1F-3F-7F-FF-FE-FC-F8-F0-E0-C0-80-00 (and bump msbs)

Allowing you store the 4 lsb's in the byte.

Quoted text here. Click to load it

Make that a factor of 16.


Rufus V. Smith
Software/Hardware Design (esp. Automation)
Home Page: http://members.aol.com/rufusvs
(still need work)

Re: Extended life of EEPROM counter?

Quoted text here. Click to load it

That may well not be an option, depending on the particular type of
EEPROM being used.  Some can only clear all bits in a whole page at
once, and then set them individually (or vice versa).  So once you're
at 0xff, you would *have* to move on to 0x00 as the next step, anyway.

Hans-Bernhard Broeker ( snipped-for-privacy@physik.rwth-aachen.de)
Even if all the snow were burnt, ashes would remain.

Re: Extended life of EEPROM counter?
$ftk$ snipped-for-privacy@nets3.rz.RWTH-Aachen.DE:

Quoted text here. Click to load it

Well, modifiy it to suit the erase state of your particular EEPROM.  All
the ones I have worked with have been erase state of all 1's.  Some allowed
you to overwrite without erasing, but only if you are clearing bits, some
automatically erased when you did a write.


Re: Extended life of EEPROM counter?
I recall an article, maybe from EDN, On allocating a 'Block' of eeprom memory
and incrementing thru
this block.
Thus if you need to write a 1 byte counter, you have N number of bytes to write
it in. Figure on two
writes for each byte, one for the counter, and one for the erase at the end of
the block. You need
to erase the block once its full so you can traverse the block to find the last
written byte. And
you cant write a counter of 0xFF, other wise you will loose the last block

So the endurance would be
(ee_endurance * Block (N)) / (number of writes)2

For a four byte array (N) you would double the endurance.


Quoted text here. Click to load it

Site Timeline