hey! i am using spartan 3E board to transmit UDP packets to my pc. I have implemented most of it, i have interfaced the PHY but there seems to be one problem, the data leaves the FPGA bt the packet is dropped at the pc's end, how i know it is that i can see the light blink bt nothing gets through to ethereal. I am assuming that my crc32 is not correct as i have double checked my other headers, the way i am sending them i.e. lower nibble first followed by higher nibble of each byte starting from Preamble -> SFD and so on. IP checksum is also correct as i have implemented it in the same manner as was said on different forums i.e. add all 16bit ip headers and then take their one's complement. This final value is our checksum.
i need to know that how should i send data to crc32 generator? i took the code from [outputlogic.com]. I am sending one byte at a time to the generator and i am calculating crc32 on the fly. I read it on some forums that you have to invert or reverse or do what to the bits and then invert or complement the final result again before transmitting . And also can you tell me how to transmit the final crc32 value i.e. lowest nibble first or what.
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