ARM Cortex Mx vs the rest of the gang

You're not thinking with HLL's in mind -- where a *tool* creates the software (how does the tool tell you, concisely, which registers it used?)

And, even if you know which registers were used, you don't know which were used SINCE THE LAST CONTEXT SWITCH!

The silicon is trivial: each load of a register (or register in a register file) forces a corresponding bit to be set in a collection of flags.

Then, a new "PUSH " opcode simply uses that "collection of flags" as the .

If you had to "manually" examine the flags (bits) in that vector and conditionally save/restore registers, the overhead of doing so wouldn't offset the cost of just unconditionally performing the save/restore.

In essence, this is what I do with my handling of the FPU context (see other post). I assume the FPU registers are NOT used and let the processor (in the NS32k example) tell me when a floating point instruction is invoked (the FPU is an optional component in the early NS32k systems; if it is NOT present, the opcodes are implemented by traps to user-supplied emulation functions) by invoking a TRAP handler.

Of course, I can use that notification (with or without a hardware FPU) to alert the OS to the fact that the additional state is being referenced and save/restore it, as appropriate.

[This only needs to happen at most once for each context switch]
Reply to
Don Y
Loading thread data ...

Of course not, although HLL-s should be pretty good at knowing what to push/pull. But I certainly consider a language broken if it creates a need for hardware not needed when using other languages.

Well and if they are not changed what, you have to mark stack frames somehow to know what exactly did you save so you can restore etc.; then even if you switch task once per ms the time to save/restore all registers is negligible (32 longwords get written to cache on a

400 MHz 32 bit processor within 80 ns...). OTOH if it is just an interrupt handler it will know what registers it uses and would save just them - and will modify them so there is no need to know whether they were changed or not.

This sounds simple enough indeed, push the register list along with the list descriptor, then use it to restore the list. But you will still have to calculate the length you allocated to save the list and this variable length might complicate the scheduler enough to cancel the benefits if not worse... hard to say by just hypothesizing.

I am even more cheeky than that on power for DPS. A task _must_ have declared it will use the FPU if it will use it, this means it gets its FPU context preserved, entirely. All 32 FP regs + fpscr etc. thing. If not, the task just won't know what the state of the FPU is; I can make it trap (a bit in the MCR) or leave it unknown (not sure which I do, trying to use the FPU when not explicitly enabled is a programming error). Quite often when I need the FPU for just a function and do not know whether the calling task will have the FPU enabled or not at the beginning the function saves the FPU on/off state, switches it "on", does its job then restores the former state.


====================================================== Dimiter Popoff, TGI

formatting link
formatting link

Reply to

Op Mon, 12 Jun 2017 16:21:12 +0200 schreef StateMachineCOM :

No. Only when you switch to an FPU-enabled task. The task dispatcher just needs to keep track of whose content is in the FPU registers, and save/restore when ownership changes.

A good task dispatcher has the FPU enable bit as part of the task context. Code that enables this bit is easily found.

(Remove the obvious prefix to reply privately.) 
Gemaakt met Opera's e-mailprogramma:
Reply to
Boudewijn Dijkstra

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.