Any Micros With MUL and no DIV?

Hi,

Are there any microcontrollers anyone is aware of that have an integer multiplication instruction but no division instruction?

Also, any with a very large speed difference between MUL and DIV?

Thanks.

P.S.--My reason for asking is that someone on comp.lang.c posted a method of division by 7 that involved multiplication by a large integer. I'm curious if it might ever be applicable ... but for it to have value a microcontroller would have to have MUL but no DIV. I've never seen a micro with MUL but no DIV. Also, on the modern ones, they seem to be comparable in speed.

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David T. Ashley              (dta@e3ft.com)
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David T. Ashley
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Sure - I want to say there are many, but the only example that jumps out at me is the AVR, possibly because I was working with it today.

IIRC the 68000 had this "feature" but it's been a long time since I wrote any code for it.

Reply to
larwe

ARM comes to mind.

Robert

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Reply to
Robert Adsett

PIC18.

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John W. Temples, III
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John Temples

On Fri, 2 Feb 2007 23:21:41 -0500, "David T. Ashley" wrote in comp.arch.embedded:

Just about every digital signal processor.

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Jack Klein
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Jack Klein

Offhand AVR Atmega series PIC 18F series

(and for MC68HC11E series, 16/16 DIV takes 41 cycles while 8*8 MUL is 10 cycles)

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Morgan Ashley (Ashiri) Stevens
Reply to
ashiri

Those that pop out to mind are: some of the MSP430 and ARM7. Also, some have incomplete DIV, such as the dsPIC and ADSP-21xx.

ADSP-21xx DSP (not really a microcontroller), for example, and the dsPIC (a microcontroller), where the DIV is incomplete and requires a loop in order to complete it. That is, if you measure 'large speed difference' as a factor of 16 or so.

Jon

Reply to
Jonathan Kirwan

6801, 6809, a bunch of the RISCs. This was/is common even among the high end RISCs like Alpha and IPF which at best have a divide approximation to get started, and then you use a few iterations of Newton-Raphson to finish the process. Multiplying by a constant (approximately by ((1/x)*2**n) where n is the word size, and is implemented as an implicit shift) is quite common when dividing by a constant, even on machines *with* a division instruction because a multiplication instruction is often several times faster and even pipelinable.
Reply to
robertwessel2

Any code that could be faster/smaller is always applicable in embedded designs, no matter how strange it looks :)

You've had plenty of example now of ones lacking DIV, but even on one that DO have Div, there can be issues with completeness. eg the 8 bit uC 80C51 has MUL and DIV opcodes, but the MUL can be used for extended precison libraries, but the DIV opcode cannot, so you will see speed deltas on higher precision maths, even in devices that appear to have both MUL and DIV opcodes.

DIV costs silicon, and is less commonly needed, so a common trade-off has been to remove or cripple it.

-jg

Reply to
Jim Granville

This last is a good point.

Especially a fully combinatorial DIV. Major pain in terms of mux and compare pieces, and lane changes along the way. I suppose that the worst case combinatorial path delay would also put a serious kink in the cycle time of the cpu -- forcing one back into thinking about sequential logic, again.

There actually _was_ one fully combinatorial FP DIV done, once. From Bipolar Integrated Tech (BIT) in Beaverton Oregon, if I recall. I've never heard of a 2nd example of that.

Jon

Reply to
Jonathan Kirwan

There are lots of processors with a mul and no div. Mul is usually significantly faster on most general purpose processors. Divides on most small micros are often not that useful in that cannot be size extended.

w..

"David T. Ashley" wrote:

Reply to
Walter Banks

We use inverted divides for constant divides in most cases where we can without losing precision in the result.

One implied point in the comment is the implied shift is generally no cost. ie a 32*32 mult used in a inverted divide leaves the result in the most significant 32 bits of the result.

w..

Reply to
Walter Banks

of

curious

micro

I suppose the trick is, to multiply with 7^-1 mod 16 (or whatever wordlength your processor has).

Wim

Reply to
Wim Ton

Quite many. AVR, most of the DSPs.

68HC11, for example. DIV is somewhat 10 times slower then MUL.

Unfortunately, the direct division has to be slow since the operations can't be paralleled. The fast division is usually done by multiplication by 1/x, where 1/x is computed by Tailor series or some other way.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

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Reply to
Vladimir Vassilevsky

I believe even the old 8031/8051 family had a multiply and divide instruction in their sets.

Dave

Reply to
Dave

I don't know if the hardware multiply unit on the MSP430 series qualifies. It's not exactly an instruction---more like a math peripheral device. It does do multiply, but not divide, though.

I think the ARM7 processors have multiply instructions, but no DIV instructions, but I'm less sure with those as I program them primarily with C.

Mark Borgerson

Reply to
Mark Borgerson

Most of the Moto/Freescale 8-bitters... HC05's and such.

John

Reply to
John Larkin

Yes, a factor of 5-10 is common, as division is more complicated than multiplication. CPUs that have similar divide and multiply speed typically use bit-serial implementations which make both extremely slow (eg. N+2 cycles for a N-bit division or multiply).

Even on CPUs that have a DIV instruction it might be faster to do divisions by a constant using multiplication. Many C compilers automatically generate special code for such divisions. However you need a fast NxN -> 2N-bit multiplier for this.

It's very common, most RISCs have MUL but not DIV. Division is typically synthesized from a special division step instruction, or a small sequence of instructions. An alternative is a Newton- Rhapson approximation using a lookup table and multiplies (this requires a really fast multiplier and is non-trivial to implement). Such software implementations are often faster than simplistic hardware dividers.

If they are comparable then MUL is seriously slow - single cycle MUL is pretty common nowadays, but the fastest DIV does 4 bits per cycle (eg. Cortex-M3), so is about 10 times as slow. Multiplier performance is logarithmic with the bitwidth while division is linear.

Also multipliers are typically pipelined while dividers are not - division could be sped up by a factor of 10-30 if a large enough amount of hardware was devoted to it. Since most programmers avoid division as it is slow on most CPUs, this won't happen...

Wilco

Reply to
Wilco Dijkstra

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