Analog Devices,TI, Cygnal 8051's?

We used the C8051F330 in the latest design. Worked like a dream, (In Sytem Debug) System Icc was as specified, at 6.4mA @ 25MHz. Only issue was the Page with ConfigByte cannot Page_erase so for EE_Emulation, data should go in the page _below_ that one. Not clear in the data, but tech support was good, and it is an obvious caveat, once you stop to think about it....

Analog Devices are moving their cores to lower-clock counts, and TI are expanding their 80C51 range, but we have not used either in a product. TI now show 18 devices, and the newest 16 bit ADCs should be cheaper than the 24bit ADC models.

Cygnal (SiLabs) have some even lower power / wider Vcc models comming - try a google on C8051F410

How is your current CU letting you down, and what specs have priority, would help get better replies..

-jg

It is a Cypress PSoC

It Draw too much current (60-80ma) Therefore generates too much heat. The C compiler does not generate the tightest code RAM or ROM. The A/D is software driven and uses too much CPU time. The PGA drifts with temperature. The Emulator does not work with statics and "local globals" Don't get me wrong the chip works, but the limitations make it a stretch for this design. Bigger PSOC chips are coming but they may not help all my issues. TI has the 430, but I am familiar with the 8051 core and the Keil compiler I am sure a 12 clock one can do the job. I need a 12 bit A/D ( I need 14 inputs so I will have to MUX) and 2 - 12 bit D/As or PWMs.

I just want to be sure a second choice will not have any problems not listed in the data sheet. If I get a new CPU and it fails my name is MUD.

Neil

If Icc really is that high, it puts them in the same area as Scenix's 'do it all in software' solution, which has quietly faded away. The PSoC part always looked a bit of a 'jack of all trades, master of none', with poor Analog specs.

TI also have 80C51 models

Many of the C8051F have wide-mux, so can handle many ADCs, the little MLP20 F330 we use, has 17 ADCs and 1 DAC, (but at 10 bits). There are bigger brothers with 12 bit ADC, and the F410 would do all you want, but may be a bit new to rush into a design.

You could also look at Maxim's MAX7651/MAX7652.

-jg

Neil Kurzman wrote in news: snipped-for-privacy@mail.asb.com:

I'm a *big* fan of the 8051 but I must admit, it took practically no time to come up to speed on the MSP430. Don't let your lack of experience with the MSP430 scare you, next to the 8051 architecture it's dead-simple.

How are the tools: The emulator, is it a quickly does it support everything. As I said, the PSoC has limitations. The compiler, the MSP430 is not common. that means the compiler is a only for it. Did they put in the work to get small fast code. I do not need a rocket, but I need to be sure it will fit. And, do not need to find every thing and more gets pushed on the stack for an interrupt. the 51 tolls and compilers are old. The weakest products have died. And there are many vendors.

for the MSP430 what are the warts? what needs special attention.

On the Analog Devices chips it looks like the A/D inputs need op amps , and the same for the REF out.

I need to be sure that I do not end up in worse shape.

Neil

The mspgcc compiler is very good. I'm told the IAR compiler produces better optimised, faster code, especially for floating point, but it costs a little more if you need to break the free compiler limit. The 51 compilers may be old, but the 51 is a bugger to write compilers for anyway, so you can expect a straightforward architecture like the MSP430 to produce cleaner code anyway. Smart pointers anyone?

- 3.3V max, and IO is not 5V compatible.

- The clocks can be a bit of a nightmare until you get used to them.

- Documentation is rather dispersed (it's all there though) - I've got 2 A4 ringbinders crammed with it, and that's only for 3 versions.

- There isn't a version with an external data-and-address bus.

- 8MHz max clock rate (but faster than a 22M divide-by-six 51).

- The internal reset can be unreliable.

- Surface mount only.

- Port IO addresses for input and output are different- this can make porting from other architectures a bit harder.

Paul Burke

Thanks for the Info. I will pass it to the EE

By the way (if any one is going to use a PSOC) The excessive current draw was caused by capacitve loading of ARef Out. Before 67ma , After

Neil