output resistance of ota

Assuming no clipping, the "large (vllotage) signal" output resistance could well be the same as the "small signal" output resistance. It depends on the load. Typically this type of circuit is driven into a buffer to, e.g. to keep the gain high, in which case, the current in the transisters don't change much. Usually one speciically designs ths stage such that that is what happens. So...

ro = Va/Id, of each transister.

Where Va is the "Early voltage". If Id is only varied a small amount, ro remains approximately constant.

Now, knowing that ro of m4 and ro of m2 are in parallel, and the expression for ro, you should be now able to calcualte the instantaenous Ro at Vx, as the current is M2 and M2 varied.

Kevin Aylward

Thanks for the answer...

Why are m4 and m2 in parallel? In large signal analysis i should consider also Vdd (in small signal analysis instead Vdd is signal- ground, so m4 and m2 are in parallel)... or not?

er...well approximatly. Technically m2 source connects through the 1/gm of m1 to ground

Only changes need to be considered. Vdd don't change. Technically there is a "DC resistance" of (Vdd- Vdrain)/ID, but this doesn't really have much relevance to calculating the "large signal" gain. As I noted, even if Vx changes a few volts, ro is still the same as its small signal value for light loads. If you take a lot of current such that this is no longer true, the stage wont work well, or at all. A lowish resistive load will kill the gain. Tyically, this stage drives a pmos.

Kevin Aylward

Thanks for the answer.... I think i have understand now.....if i consider large signal analysis, all voltage and current sources that don't vary in time (as Vdd,Vss,ecc) are ground signal (for voltage sourcer) or open circuit (for current bias sources), is it right?