Audio amplifier (part 2)

I don't think so. It looks like you have a basic understanding of what you are doing. Of course, that strongly depends on what you are trying to do.

You have two separate but interconnected problems. How to change the bias point for the two output transistors, and how to produce a zero signal output of zero volts.

If you change R1 and R2 at the same time, you should be able to change the bias point and still maintain the desired output voltage. But this circuit depends strongly on component matching and power supply voltage stability. More practical versions use negative feedback to correct for variations in components and supply voltages.

First, you should make a functional list of "improvements" (what would define a functional improvement in the operation). Then you are in a better position to consider circuit changes and how they interact with those functions.

First, I think you should explore frequency response. Your test waveform is 100 Hz. Change that to 10,000 Hz and I think one of the weaknesses of this circuit will start to show up. Both of your output devices have lots of turn on drive, but no turn off drive, so once they are on, they will be very slow to turn off. This will produce increasing distortion and higher bias current as frequency rises.

You *really* need to add resistors across the base/emitter of the output transistors, otherwise speed will be an issue, especially once you put this thing in an overall feedback loop.

I would tend to make them on the real low side, considering driving 3055's to thier max needs 1A. Losing say, 100ma in these resister would be, 0.8/.1 = 8 ohms. Say, 10 ohms. However, this gives a tad of power in the drivers, so you may want to consider anything from 20 to 100ohms. I wouldn't go over

Kevin Aylward snipped-for-privacy@kevinaylward.co.uk

Thanks John for your help.

Do you think it is possible to change the design in order to have only one potentiometer to change the bias of the transistors, instead of changing R1 and R2 ?

For the negative feedback, I imagine that I have to measure the DC level at the load resistor, compare it with 0, negate it and re inject it somewhere in the input bias, but I do not see how ...

I have explored the frequency response. It is still ok at 10k and even more . Pehaps the spice model of my components are too ideal. I should put some parasitic inductances and capacitors ... or find other models ...

Olivier

Thanks Kevin. Yes you are right ! see:

Is it because there are too many charges into the base ? And with the resistors, it is easier for the charges to go out of the transistor ?

Olivier

On Wed, 22 Oct 2008 17:45:04 +0200, Olivier Scalbert wrote:

--- Not necessarily.

As John Popelish noted, using negative feedback and providing a little bias when the input is at zero volts will force the output to be at zero volts during those times.

Run this to see how it could be done:

Version 4 SHEET 1 1476 680 WIRE 512 -144 -208 -144 WIRE -128 -64 -576 -64 WIRE 224 -64 -128 -64 WIRE 368 -64 224 -64 WIRE 224 -16 224 -64 WIRE -208 16 -208 -144 WIRE 368 32 368 -64 WIRE -576 48 -576 -64 WIRE 0 112 -16 112 WIRE 96 112 64 112 WIRE 224 112 224 64 WIRE 224 112 176 112 WIRE 320 112 224 112 WIRE -128 160 -128 -64 WIRE -576 176 -576 128 WIRE -576 176 -672 176 WIRE -352 176 -448 176 WIRE -208 176 -208 96 WIRE -208 176 -272 176 WIRE -160 176 -208 176 WIRE -16 192 -16 112 WIRE -16 192 -96 192 WIRE 368 192 368 128 WIRE 512 192 512 -144 WIRE 512 192 368 192 WIRE -160 208 -208 208 WIRE -576 224 -576 176 WIRE -448 224 -448 176 WIRE 368 256 368 192 WIRE -208 272 -208 208 WIRE -16 272 -16 192 WIRE 0 272 -16 272 WIRE 96 272 64 272 WIRE 224 272 176 272 WIRE 320 272 224 272 WIRE 224 320 224 272 WIRE 512 320 512 192 WIRE -576 448 -576 304 WIRE -128 448 -128 224 WIRE -128 448 -576 448 WIRE 224 448 224 400 WIRE 224 448 -128 448 WIRE 368 448 368 352 WIRE 368 448 224 448 WIRE -672 528 -672 176 WIRE -448 528 -448 304 WIRE -448 528 -672 528 WIRE -208 528 -208 352 WIRE -208 528 -448 528 WIRE 512 528 512 400 WIRE 512 528 -208 528 WIRE -672 592 -672 528 FLAG -672 592 0 SYMBOL voltage -576 32 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 15 SYMBOL voltage -576 208 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value 15 SYMBOL voltage -448 208 R0 WINDOW 3 24 104 Invisible 0 WINDOW 123 20 110 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value SINE(0 1 20000) SYMATTR Value2 AC 1 SYMATTR InstName V3 SYMBOL res 496 304 R0 SYMATTR InstName R1 SYMATTR Value 4 SYMBOL res -256 160 R90 WINDOW 0 -31 55 VBottom 0 WINDOW 3 -26 57 VTop 0 SYMATTR InstName R2 SYMATTR Value 100 SYMBOL res -192 112 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R3 SYMATTR Value 510 SYMBOL res -224 256 R0 SYMATTR InstName R7 SYMATTR Value 82 SYMBOL nmos 320 32 R0 SYMATTR InstName M1 SYMATTR Value FDB2532 SYMBOL pmos 320 352 M180 SYMATTR InstName M2 SYMATTR Value HAT1072H SYMBOL diode 64 96 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName D1 SYMATTR Value 1N4148 SYMBOL res 208 -32 R0 SYMATTR InstName R6 SYMATTR Value 1000 SYMBOL res 208 304 R0 SYMATTR InstName R8 SYMATTR Value 1000 SYMBOL Opamps\\\\LT1007 -128 128 R0 SYMATTR InstName U1 SYMBOL diode 0 288 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName D3 SYMATTR Value 1N4148 SYMBOL res 192 96 R90 WINDOW 0 -31 55 VBottom 0 WINDOW 3 -26 57 VTop 0 SYMATTR InstName R4 SYMATTR Value 170 SYMBOL res 192 256 R90 WINDOW 0 -31 55 VBottom 0 WINDOW 3 -26 57 VTop 0 SYMATTR InstName R5 SYMATTR Value 170 TEXT -640 552 Left 0 !.tran .001 uic TEXT -440 552 Left 0 !;ac oct 256 20 20000

JF

Yes, though it might produce other problems. The most common way to produce the approximately 3 diode drop bias voltage between the driver bases is to multiply the base emitter drop of an additional transistor, with the multiplication ratio set by a potentiometer (instead of connecting 3 diodes in series).

The Vbe multiplier is described in this reference:

You add a potentiometer in series with R1 and R2 to make the ratio variable over a small range to set your output device bias current. You choose the resistor value to make the total current through the resistor divider to be about

Unfortunately, this bias generator eliminates the feed point you are using for the amplifier that best balances the input offset from zero. You could get his back by using the adjustable Vbe multiplier to only replace the pair of diodes on one side of the feed point, making only the drop of that pair adjustable.

Or connect the output load in series with a capacitor so that it is not possible for the amplifier to pass DC through the load. If the load does not need to have a connection to the supply ground, you might use a pair of capacitors, in series across the total supply, and reconnect the grounded end of the load to the common point in that series string. This places a predictable DC bias across he capacitors, and they help filter the real supply.

Since your amplifier stage has a gain very close to 1, just adding more negative feedback would not do much good. You also need to add gain to that operation. Say an opamp connected as an inverting integrator. But normally, this additional gain and inversion is produced by additional transistors that make up a gain block ahead of this unity gain output current booster.

Including the transistor collector currents? I think you should start to see some distortion in the current wave forms with this configuration.

Are you using the models that came with LTspice?

A couple suggestions that would make the circuit more practical:

Connect the lower transistor pair without the 0.5 ohm resistor between them. keep that resistor between them and the output node, so it is more similar to the upper darlington.

Add a pair of 10 to 100 ohm resistors between base and emitter of the two output transistors to make them turn off faster.

Thanks John, I need some times to digest all you told me !!!

Olivier

"Too many charges" is not quite the right concept.

It is necessary to store charge in the base emitter junction to turn the transistor on. It is necessary to remove that charge to make it turn off quickly, after it has been on. The junction will consume that charge, eventually, if you do not drain it out, but that is a component and temperature dependent process and most applications cannot tolerate the long and variable self discharge time.

To cool ! Thanks John.

Some points:

- I am stupid as I focus on extracting DC from output .. instead of comparing output with input !

- I have never played before yesterday with LTSpice. It is incredible. You give me a circuit in ascii, and I can run it, modify it ! Wow !

- I do not know how Mosfet works. In fact they afraid me a little. Your amplifier as a gain of 5. Is it R6/R4 ?

- does it "sound" good ?

Olivier

--- They are, in effect, voltage-controlled resistors with the drain-to-source resistance being lowered more and more as the gate voltage more and more closely approaches the drain voltage.

Try this:

Version 4 SHEET 1 880 680 WIRE -32 0 -368 0 WIRE -32 32 -32 0 WIRE -32 128 -32 112 WIRE -80 208 -272 208 WIRE -368 240 -368 0 WIRE -272 240 -272 208 WIRE -368 368 -368 320 WIRE -272 368 -272 320 WIRE -272 368 -368 368 WIRE -32 368 -32 224 WIRE -32 368 -272 368 WIRE -368 400 -368 368 FLAG -368 400 0 SYMBOL nmos -80 128 R0 SYMATTR InstName M1 SYMATTR Value FDC2512 SYMBOL voltage -368 224 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 12 SYMBOL voltage -272 224 R0 WINDOW 3 8 104 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value PULSE(0 12 0 1) SYMBOL res -48 16 R0 SYMATTR InstName R1 SYMATTR Value 1 TEXT -346 392 Left 0 !.tran 1.1 uic

Plot the current through R1 and the voltage on the gate as a function of time and you'll see what I mean.

Just for fun, you might also want to move R1 to between the drain and ground and do the same plot as earlier.

---

--- No, R3/R2

---

--- Dunno, but it should. Do an AC analysis on it and you'll see it's flat to within about 0.5dB out to around 200kHz or so.

I haven't found out how to do an FFT in LTspice yet, so there may be an itermodulation problem lurking in there somewhere.

Also, Linear touts the LT1007 as being the lowest-noise opamp available. I'll have to build one and find out what it sounds like!

BTW, I just picked those MOSFETS kind of at random from the list of available ones from LTspice, so they may not be able to dissipate the kind of power needed for and audio amp.

JF

--- ^^^^^ Oops... source

JF

Basically yes. Essentially, there is a big cap. The driver transistor can charge it up, but without a turn off it, can't discharge much.

Personally, I prefer full class Ab drive all the way, that way you can source and sink large currents to turn the thing off!.

Kevin Aylward

Hi John,

For the FFT, just right click in the simulation screen and select FFT in the popup menu.

Olivier

Also increase stop time in the simulation box to have more points. BTW how to convert harmonic levels in FFT to distorsion in percentage ?

Olivier

Ok thanks ! Olivier

Hi,

In fact, how do you compute R5 and R8 ? Olivier

--- Empirically. ;)

In the simulator, what I did was (with 0V into R1) arbitrarily choose R6 and R8 at 1000 ohms and then adjusted R4 and R5 for 30mA of current through both MOSFETs.

In the real world, what I'd do would be to replace the resistors with

Then, before applying power I'd make sure Vin was grounded and the pots were cranked to zero ohms between the gates and the diodes.

After that, I'd apply power and crank one of the pots until I got 30mA through the load and then crank the other pot until the current through the load fell to zero.

That 30 mA will now be in both MOSFETs and will be the current causing the stage to run AB which will kill crossover distortion. Also, the load will be DC coupled to the input and will be at zero volts with zero volts on Vin, which is what you want.

There also probably needs to be some soft-start circuitry in there somewhere to protect the load and the MOSFETS against power-on transients from the opamp. Something as simple as a relay momentarily shorting the opamp's output to ground during power-on should work:

JF