8 switches

But how do I answer TWO doors at the same time????

see alt.sci.clone ;-)

OOpps! I've got the wrong logic in my truth table there: for NO switches with pullups, you'd need this:

addresses data (hex) binary hex 11111111110 3FE 0xFE 11111111101 3FD 0xFE 11111111011 3FB 0xFE 11111110111 3F7 0xFE 11111101111 3EF 0xFE 11111011111 3DF 0xFE 11110111111 3BF 0xFE 11101111111 37F 0xFE

Cheers! Rich

I have a refinement for your schematic: The reference divider has to distinguish between 0 and 40% of supply (to tell 1 switch from zero) so I think the lower reference level should be about 20% of supply. The second decision distinguishes between 40% and 58% of supply (one switch versus two switches), so the reference should be about half way between those, or 49% of supply. This case has less noise margin than the first one (+- about 10% versus about +- 20%), so the threshold has to be pretty well centered to maximize noise margin and resistor tolerance.

So here is your schematic repeated with the reference divider altered to make approximately those choices:

Vcc--+--------+---//---+ | | | | [10k] [10k] | | | | O| O| | O| O| | |S1 |S8 [51k] +---//---+ | | | | Vcc V+ | | | | | | | [R] | +--|-\\ | | | | >--+ +--------|--|+/ | | | | [30k] | LM393 | | | | +--------|--|-\\ | | | | >--+-->OUT | +--|+/ | | | [20k] [6k8] | | | | | | | GND>-+--------+---+------->GND

I think this provides enough margin for 5% resistors to work well enough, if the switch lines are not subject to much noise pickup. The O.P. might need to add a little filter capacitance across the 6.8k to reduce hum.

--- OK.

From one of your previous posts, I like your idea of referencing the switch divider to ground instead of to Vcc, and your choice of resistors, which _does_ give the largest difference in voltage between one and two resistors switched in. Although, with a 3V supply, the difference is only about 15mV more than with equal-value resistors!

With the switching divider looking like this:

E1 | +------+ | | [R2] [R3] | | O| O| O| O| | | +------+------E2 | [R1] | 0V

and, with a 3V supply and your resistors, we have, for a single resistor switched in:

EIR1 3V * 6800R E2 = ------- = -------------- = 1.214V R1+R2 10kR + 6800R

and for two resistors switched in:

E1R1 E2 = ----------------- = 1.729v R1 + (R2 || R3)

Now, since the upper limit of the common mode voltage range for the LM393 is Vcc -1.5V, that's 1.5V for a 3V supply. Since the output voltage of the switch divider will rise to 1.729V when two switches are closed (and higher than that if more than two switches are closed) we have to make sure that the higher output voltage from the reference divider stays below 1.5V in order for the comparator to work properly.

If we make a chart of where the system voltages lie in relation to each other, amplitude-wise, we'll get something like this:

Vcc----------------3V

V2sw-------------1.73V

Vcm--------------1.5V

Vhi--------------??

V1sw-------------1.21V

Vlo--------------??

GND---------------0V

If we make Vhi equal to 1.4V, that'll give us 100mV of headroom to the common mode limit, Vcm, which ought to be plenty, and it'll also be higher than the one-switch output voltage, V1sw, which is what we want. Then if we make the difference between Vhi and V1sw the same as the voltage difference between V1sw and Vlo and round everything off, the chart will look like this:

Vcc----------------3V

V2sw-------------1.7V

Vcm--------------1.5V

Vhi--------------1.4V

V1sw-------------1.2V

Vlo--------------1.0V

GND---------------0V

and with 100µA in the reference string, the circuit will look like this.

Vcc--+--------+---//---+ | | | | [10k] [10k] | | | | O| O| | O| O| | |S1 |S8 [16k] +---//---+ | | | | V+ | | | | | [R] | +--|-\\ | | | | >--+ +--------|--|+/ | | | | [3k9] | | | | | +--------|--|-\\ | | | | >--+ | +--|+/ | | [10k] [6k8] | | | | GND>-+--------+

Now, since we're using 5% resistors, the worst thing that could happen is if their tolerances let the comparator input voltages step on each other.

I've worked it all out, but rather than do a lot of extra typing, I've posted my handwritten worksheets to abse.

-- John Fields Professional Circuit Designer

John Popelish wrote: Oops. I need to fix the picture to put Vcm above V2sw.

Nice analysis with practical considerations (though, if I were really going to go with a 3 volt battery supply, I think I would go with the low voltage version of the dual comparator). I understand why you are pushing the noise margin of Vhi to stay under the common mode voltage limit, but why do you not center Vlo between GND and V1sw? It seems to me that this reduces the tolerance limit for the lower resistor in the reference string. Is there some advantage of raising this voltage that I missed?

Perhaps a better solution to the common mode limit would be to reduce the common switch resistor a bit more. Something like 4.7k helps quite a bit. It lowers V1sw (=.959 vs. 1.2 or down 20%) more than it does V2sw-V1sw (=.495 vs. .50 or down 1%). The 1% drop in V2sw-V1sw is more than compensated for by making the whole swing usable.

The list changes to:

Vcc---------------3.000V

V2sw--------------1.454V

Vcm---------------1.5V

Vhi---------------1.206V

V1sw--------------0.959V

Vlo---------------0.480V

GND---------------0V

This provides .248 volts margin on both sides Vhi, while operating below Vcm for V2sw. Vlo still has .480 volts margin on each side.

Vcm won't interfer till the battery falls to 2.41, assuming the comparator still works at all.

Of course, if the circuit will run from a 9 volt battery, then I would go back to the 6.8k common resistor and have huge noise margin and maximum resistor tolerance.

Are we having too much fun with this simple circuit, yet?

This has been an excellent exercise demonstrating how a concept (even one as simple as a couple voltage dividers) can evolve just by considering various constraints. But until the O.P. comes back with some guidence as to what constraints actually apply to his problem, I guess I am done. I have enjoyed the process.