x-Chapters, 4x.3, 16 more pages about TIAs

Announcing a useful x-Chapter DRAFT section.

Compensation of TIAs wasn't discussed much in AoE III, 8.11, pages 537-555. Mentioned briefly in 4.3.1.C, we assigned the topic to Chapter 4x. Here's x-Chapter section 4x.3, which adds 16 pages to 19 TIA pages in AoE3.

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(This is a partial repost in a new-thread, from thread, "RF transistors for PD cascode" where George Herold was considering using a cascode input for TIA photodiode amplifier. There I argued that when working to reduce high-frequency e_n Cin noise in a TIA, the cascode isolation approach works well only at higher input current levels, where you can maintain the cascode gain (fT) of the transistor, end even add additional bias current. But at very low currents, the bootstrap approach can work better.) See details in AoE III, 8.11, pages 537-555.

Beside discussing compensation, we show a few useful tricks. And 4x.3.7 introduces an amazing TIA configuration, which covers a dynamic signal range of 10^7 or more, with a single TIA op-amp. During discussions here on s.e.d., two other approaches came up. See 4x.3.9 using a bootstrap, including a 1-meg TIA with 1MHz bandwidth. And 4x.3.10 with a cascode BJT. There we see again the struggle to maintain wide amplifier bandwidth when using a cascode at currents below 1 to 10uA, also see fT discussion in 2x.9 to 2x.11

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--
 Thanks, 
    - Win
Reply to
Winfield Hill
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One trick that I've used for gain switching is to have two cascode transistors. Both emitters go to the photodiode, but the collectors drive separate amps with different gains. Wiggle the transistor base voltages to decide which path is active.

Reply to
jlarkin

Yessir. Fleshed out in detail in 4x.3.10, but I didn't know (or remember?) you had also come up with the idea. I combined it with a JFET bootstrap; BJT e_n gets high at low currents.

Your unusual diode scheme is explored in 4x.3.9, where we show a 1M-ohm 1MHz version. That's not possible with the super-wide-range simultaneous- outputs scheme in 4x.3.7, due to JFET capacitance.

Lots of good reading for you in there, John.

--
 Thanks, 
    - Win
Reply to
Winfield Hill

Here's an emitter-switched version:

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We designed this for a big semiconductor-equipment company. It worked great, so they stole it and did it themselves. Turns out they are notorious, even proud, of doing that.

Reply to
jlarkin

What was the capacitance of the PD in that unit? I see you paralleled two BF862 bootstraps.

--
 Thanks, 
    - Win
Reply to
Winfield Hill

Hey, Mouser has it now.

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UV enhanced, to snoop a plasma discharge through a quartz window.

Fun while it lasted.

Reply to
jlarkin

TIA = Transient Ischemic Attack

I can see why they wouldn't be mentioned in an electronics book.

--

  Rick C. 

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Reply to
Rick C

The things we learn about as we get older.

--
 Thanks, 
    - Win
Reply to
Winfield Hill

As I get older I begin to have a better idea of what is going to kill /me/.

An idiot reporter once asked Michael Caine (the actor) what it was like being 60. Caine, who is pretty down-to-earth and sensible, merely said "Better than the alternative".

Reply to
Tom Gardner

Thanks Win, lots to read. I think you've posted some of that before.

I've got to measure the low level response of the cascode. At low currents, say 10 nA, does the transistor not turn on? most of the photo current goes into the base?

George H.

Reply to
George Herold

Again thanks, I can groove on the first figure. We use this diode connected transistor as a temp sensor. I said, let's put in a current range switch and then you can crudely calibrate the sensor by measuring the forward voltage at different currents. (1-10-100 uA) is the good range. The non-ideality is ~1%, And I assume is related to current gain. Anyway, at low currents (delta V between 10 nA and 100 nA) the non-ideality is worse. ~5% I think. (1.05)

George H.

Reply to
George Herold

Looks like the second part number in footnote 18 should be CPH6904. (Also, footnotes 18 and 30 are perhaps slightly repetitive.)

? David

Reply to
David Nadlinger

What kind of transistor? For good logarithm conformance, the low-noise types are preferred (like, BC550C).

Reply to
whit3rd

It'll be turned on.

No. See AoE3 Figures 2.41 and 2.42 on page 92. The latter shows a "typical" transistor with beta = 350 at 10nA. See measured beta plots in Figure 8.39, where traces 32, 35 and 38 show flat beta down to 1uA, and they will continue to have plenty of gain, even down to below 1nA. Or see Gummel plots in Figs 2x.72 and 2x.73, if you have it, with gain at 10pA.

Now see Figure 8.85, which shows the problems with using a cascode connection, rather than a JFET boostrap, to deal with high PD capacitance. Trace 38 was a 2n5088, a good transistor to use at low-currents. Its curve is on a trajectory for fT=10MHz at 50uA. fT is proportional to Ic, in that region, so we can estimate its fT would be 2kHz at 10nA. Your PD amplifier would start losing gain above 2kHz if the signal was 10nA.**

OTOH, with a say 10M feedback resistor, you'd still have a 100mV signal, and keep your gain out to the fc bandwidth, which could be 400kHz, if you used a JFET bootstrap with a 50MHz opamp.

A typical resistor's self capacitance might be 0.15pF, which would limit your fc bandwidth to 100kHz with 10M. To get to 400kHz, you can use a feedback-resistor trick in Figure 8.80.C, and set the trimpot with the fixture in Figure 8.91. Or you could be satisfied with 100kHz, given that your en-Cin noise will be rising in that region anyway, plus you could get away with only a 5MHz opamp, assuming Cin

Reply to
Winfield Hill

TIP-32c (pnp TO-220) collector stuck to ground.

George H.

Reply to
George Herold

Probably low-ish lifetime for carriers in the base, you'd see some emitter resistance at higher currents. That's typical for power transistors. Good thermal time constant, easy attachment through the tab, though.

Reply to
whit3rd

One caution: the capacitance of a CMOS switch isn't all to ground, some of it's to the supply rail. The V+ supply needs to be very quiet.

17 pF is kind of a lot of c to hang on the summing point of an opamp.
Reply to
jlarkin

Hi Win, wow thanks so much for the help and interest. I think i've finally got my head around the transistor GBW (f_T) as a function of collector current.

I did the following series of experiments with big pin-44 PD, opa2192 opamp, ~15 V of bias on the PD and 10 Meg ohm TIA resistor. I'm looking at the step response (blinking LED) and choose the output amplitude to always be 600 mVp-p... three scale divisions on 'scope which lets me guesstimate time constant (TC) as time to 2/3rds of max.

1.) straight TIA, ugly near turn on, ~200 us TC.

2.) with cascode (2n3904) ~300 us TC... linear rise of voltage with time (not at all, a one pole response.)

3.) cascode with 100 Meg bias R. Sweet one pole response, TC = 50 us.

4.) cascode, with bias and with bootstrap (of PD), better and better one pole and ~10 us TC

5.) remove bias R, cascode and bootstrap. ~20 uS TC, slow turn-on (not one pole.)

6.) bootstrap alone. Nice one pole, ~10 us TC (maybe a tinch faster than the full cascode/ bias/ bootstrap.

This is all very encouraging, and I assume expected by all the PD-front end experts.

I'm going to try the 'full monty' (cascode/bais/ bootstrap) with 1 meg FB. fun stuff.

George H. (who wonders why he didn't try the cascode years ago.)

Reply to
George Herold

Am 13.09.19 um 16:36 schrieb snipped-for-privacy@highlandsniptechnology.com:

I have used sth. similar for AGC in a Driscoll oscillator. One of the 2 cascode transistors diverts some of the current to /dev/nul.

cheers, Gerhard

Reply to
Gerhard Hoffmann

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