Why are SSR so slow?

I did some experimenting with the vo1263

And the LH1262C.

I found if you give them a jolt near there max peak rated current it will improve the on time. You then have to bring the current source back down to a reasonable continuous level to maintain the desired Vgs over temperature range. I wound up using a pulsed current source then switch it out and use a temperature controlled current source.

Depending on the duty cycle you could do something along those lines,minus the temperature controlled CS.The appnote below has other suggestions for improveing rise/fall times.

Your SSR has integrated FETS the ones I used were for driving external FETs but it should work the same.

It all wound up being to much of a pain in the ass, so I just built an isolated supply using a cheap murata pulse XT to power a PIC10F and discrete zero crossing detector and a floating FET driver.

Here is an application note I found useful from Vishay.

That's a teeny one, I need several amps at up to 40V.

That one I don't know. National's site didn't find it either.

The jolt would be a problem in my case. What I want to try is replace a small board with a LabJack and PWM some sort of electronic switch with it. If I have to provide separate opto-drivers plus maybe a buffer and whatnot I might as well design the whole circuit as usual.

The duty cycle would need to vary between 50% on to 95% on.

Nice app note, although they should get into the habit of running a spell-checker before release :-)

All those methods they present are great but why not do something more elaborate? For example, run a little charge pump in there that builds up a voltage in a small external ceramic cap that gets hooked up via a 5th contact and input-ground. It would build up charge during the first on-phase so that all the following transitions would be fast. Should not be a big deal inside a chip.

--
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The floating gate driver circuit is powered by a pv link, the prime source of power being the logic input itself. The input is milliwatts and the pv link is inefficient, so there's not much power available for the gate drive electronics to run from. Some parts do manage a millisecond on and off, not much better.

You could use my dual-optotransistor totem-pole driver, but it will need some sort of power source on the fet side, possibly bled from the load power. Or use one of the new fet drivers that has a built-in honest-to-goodness power isolator. Oh, forgot, your budget is probably

16 cents or something.

John

On a sunny day (Sun, 30 Aug 2009 10:50:16 -0400) it happened Hammy wrote in :

A nice paper. The drawing in fig 16 (page 9) is insane however, the collector of Q6 should just go to the gate of Q4. Same for Q3 Q2, this sort of drawing sucks, just a whole detour around the place... hate to see his PCBs.

I had hoped that by now someone would have come out with a device that has a charge pump, so that at least after one or very few high phases some more oomph would be available. But ...

Actually not, this one can cost $10-$20 for the SSR function. But if I need to supply some regulated 15V or so at tens of mA I might as well go discrete like I used to. Simple 4N-whatever, then a MOSFET driver, done. I wanted to avoid the extra power supply. Guess that ain't in the cards.

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On the first page, right side column, I read "...the illustration in Figure 1 should speak for itself. One can see a mechanical relay with a current handling capacity of 25 A and a power MOSFET with a current handling capacity of 30 A side by side."

I can find Figure 1, just fine. On page 2. But I certainly don't "see" a mechanical relay and a power MOSFET side by side, there.

On page 2 they say, "The detector or output side of the VO1263 can be thought of schematically as a matrix of series photodiodes similar to what is ilustrated in Figure 1."

Now that I do see in Figure 1.

I wonder where the first "Figure 1" went to.

Jon

P.S. I see some nice "product placement" of LeCroy on the scope charts.

Um. Figure 16 doesn't have a Q6. You are talking about Figure 17.

And in Figure 17, I would have drawn it this way (including what then appears to be a question to me):

That gets across things very quickly. There are two voltage lines with separate current limits set via Q3/R3 and Q6/R4 and the collectors are wire-OR'd to the common gate line of Q2/Q4. What then appears to be a question is that Vdd must be on the same side of ground as Vcc -- Q4 is NMOS and Q6 is NPN, just like Q2 and Q3, respectively. I had imagined from their use of "bipolar" and the presentation of Vdd 'below ground' on their diagram, that Vdd would be on the other side of ground.

Jon

What's the load voltage?

Can you afford to steal a little leakage current when the fet is off?

John

On a sunny day (Sun, 30 Aug 2009 17:24:35 GMT) it happened Jon Kirwan wrote in :

You are right!

But did you notice he took the emittor of Q6 from the OPPOSITE source resistor? The way you draw it is OK.

Yes, and not to mention the mysterious ground symbol in that diagram... Oh, well, just as long as you do not connect it to earth it will probably be OK..

The whole thing looked screwy, so I'm not surprised.

Well, I hope so. Otherwise, I'd need to improve my drafting skills. ;)

I must have missed that. Where?

OK..

I'm still wondering about Vdd, though. Being a mere hobbyist with sorely limited experience, I can't say for sure. But it sure looks like they have just used cut and paste and got it all wrongly said.

Jon

Well yes it's not the most intuitively structured pdf. It does provide some useful information. Compared to inductor datsheets it's a wealth of information.

What I did was drive one channel with a 100mA pulse for about 0.5mS or so then had the current source take over to maintain 11V gate to source. I also used the second channel to drive a small NTS4001 or

2n700x FET to snap off the primary fets in uS time. In the pdf they use a passive approach for discharging the FET Cin, or a JFET. I did this all a while ago so my times and currents probably aren't 100% accurate.

There were a few things I didn't like about them though they require about 8 to 15mA CC to maintain 11Vgs (Very temperature dependent) and if you want snappy performance for even moderately sized mosfets (40nC) (snappy performance for an SSR is on times below 1mS) the drive cct can get a bit complex and require to many parts. This is why I just wound up building a small isolated supply it was cheaper and used only 2 to 3mA.

On a sunny day (Sun, 30 Aug 2009 18:18:51 GMT) it happened Jon Kirwan wrote in :

I was referring to that ground symbol. It is there probably for some simulation. When used as a solid state relay to switch AC, I would not use 'Vdd' and Vcc' either. Just AC1 and AC2 perhaps.

Just a matter of opinion. :-)

Do you have any examples of waveforms posted on your web site?

I needed a fast optocoupler a while back and analyzed all the different configurations in SPICE. Your totem pole configuration was one of the slowest. I suspect it was due to the top element acting as a weak current source instead of an emitter follower as you might conclude from looking at the schematic.

If you have any speed comparisons vs conventional hookups, this would be an ideal time to show them.

The circuit is so simple it shouldn't take more than a few minutes to set up and photograph. Since you are the inventor, we should expect the results to be the best possible with that configuration.

Normally between 20V and 40V, must be able to go to about 60V without damage.

Oh yeah, I can steal almost all the current I want. Well, as long as it's less than half an amp or so.

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I can't help what you conclude from a schematic.

Not for me. I have other things to do today.

How would the parts know they are performing for "the inventor"?

I never made any speed claims, so I don't have to defend it. You can always speed it up some by adding b-e resistors on the phototransistors, if that matters to you. Or use a GHz laser/pin diode/TIA coupler instead.

The virtues of this circuit are economy, simplicity, DC coupling, and zero static power dissipation. Joerg could derive the floating supply from the load, with a simple diode-resistor-zener thing maybe.

ftp://jjlarkin.lmi.net/FetDriver.jpg

Use it as you will.

There are also some interesting analog things you can do with 400 volt couplers in the totem-pole config.

John

On a sunny day (Sun, 30 Aug 2009 14:24:53 -0700) it happened John Larkin wrote in :

Well, all transformer avoiders :-)

How 'bout a keyed 555, driving a small 1:1 pulse transformer, on the other side a simple diode detector, and RC network (say AM detector).

For a carrier of say 100 kHz, 10 uS, and a RC over 10 periods it is already 100 uS. In place of the 555 you could use a single transistor oscillating at 10 MHz, RC over 10 periods secondair, makes 1 uS, 100 MHz makes 100 nS.

For example:

20 MHz out from the FPGA [you have] via some HC buffers driving a 1:1 transformer, on the other side a diode with RC network on the MOSFET gate. Beats you in component count, speed, and needs no secondary supply. Can wind it yourself on a tiny ferrite core, 5 turns + 5 turns, 1 turn per volt.

hehe :-)

Pffbt, well then that's easy enough even I can do it. And did,

Tim

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A follower from a current, albeit photo-induced is still just a current (beta ;-)

Try driving the LED harder.

Of course not ;-)

Bwahahahaha! Same old shit!

...Jim Thompson

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The second sign of senility is touting your company\'s wonderful
circuit designs as your own, while posting amateur crap on S.E.D

The third sign is acting like Polly Prissypants :-)

Sure, I can do that as well or I should give back my degree :-)

But: I was trying to avoid a circuit board since I already have a device that can drive the signal, at 3.3V and a few mA. It would be nice to be able to just lash up a SSR, sans other electronics. But I guess not :-(

--
Regards, Joerg

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