VON NEUMANN VS HARVARD

It has always been possible to return structures in C. You cannot return an array from a function but you can return a structure containing an array (as perhaps it's only member) or a pointer that points into an array.

Robert Gamble

That compiler was broken. The C89 standard allowed passing and returning structures.

You can't. Not directly.

Close. Just declare a structure with the array as an element ant return that. Just be aware that it means the array is getting copied around which can be rather inefficient.

struct arr_ret { int a[5]; };

struct arr_ret foo(int*);

Generally I would pass a pointer to the first element of the return array instead, just like memcpy, strcpy etc.

You're question is about C and that is fine here and we don't mind a bit of banter so I've re-instated the cross-post. Just remove the cross-post if the thread drifts off C on to other things.

"Robert Gamble" writes: [...]

No, not always. That capability, along with structure assignment, was added not long after K&R1 (Kernighan & Ritchie, _The C Programming Language_, 1st Edition, which was the de facto language definition before the 1989 ANSI standard was published).

Though I suppose in this business a few decades or so is close enough to "always".

The problem is even more severe _because_ the processors are so much faster than memory. Modern processors fetch more than one instruction from memory (memory is fetched in cache line increments) at a time anyway, Harvard isn't needed for that.

I thought this might have been the case but I don't have a copy of K&R1 and wasn't able to quickly confirm this with a web search before I posted. Thanks for the information.

Robert Gamble

There is a limited number of instruction codes which can be executed in one cycle. For each memory space, extra instructions are required to access it (move, test, add, substract, etc). This leaves less room for other instructions and may force the designer to make some instructions longer (which will take 2 or more cycles to fetch and execute).

C has become more than just a language. Part of the power of C lies in the standard libraries. Show me a strcpy function which can take a pointer in the instruction memory or data memory as the source on a Harvard style CPU.

This problem pinpoints the problem you'll run into when you are going to take a harvard cpu beyond plain number crunching. Working with strings is a nightmare on a Harvard CPU if you want to use both constant strings and variable strings. If you have enough memory, you might choose for copying the constant strings into data memory, but this might be limited in size or slow (like on any 8051 derivative).

Then tell me why I need pragma's and non-C extensions when writing C code for Harvard CPUs to tell the compiler where the data should be stored & fetched?

You don't need any pragmas. I've never needed any pragmas when using the following compilers:

1. AVR gcc
2. HITECH C
3. Keil
4. CC5x
5. CSS

So, what compiler are you using and why do you need those pragmas? I've only ever needed pragmas for storing data when using a Von Neumann CPU: the 8051.

Agreed but Nico was saying that the one with the single bus is faster. What I'm saying is, even granting him that his instructions are cached, it will only make it just as fast as a Harvard machine. I don't see how he can say that Von Neuman machines are faster "because" of the unified memory space.

For each memory space? You only access data in data space, you don't access data in instruction space (well, on a Von Neumann machine you can of course). No extra instructions are required. On pure Harvard machines, jumps, branch and gotos only operate in instruction address, read/write data access only operate in data address - actually, just like a Von Neumann machine except instruction and data address are separate. And most Harvard CPUs are typically also RISC CPUs - they only have a single instruction size. I have personally never seen a Harvard CPU with multiple instruction sizes, can you show me one?

Because the data and instruction memory are seperate CPU designers can use different sizes for them. This allows Harvard machines to *always* be able to be designed as a single-instruction-per-word RISC machine.

while

Bullshit. I have a Pentium2 motherboard that uses simple SRAMS as L2 cache. Those chips only have a single read/write port (I would know, I salvaged them when my mobo died). Caches, even today, are not usually multiported. Don't know about newer chips but even as late as the Pentium3 the cache is not multiported.

Not necessary (this proven by the fact that in the real world caches are in fact single ported). You only load cache when there's a cache miss (or predicted cache miss). When a miss happens the data is not available anyway so instruction processing is temporarily stalled or on threaded CPUs switches to a thread that doesn't stall.

When? Caches were single ported on most CPUs up to 2001. And on most CPUs they are still single ported to this day, at most they have separate read and write port. What CPU implements this massively multiport cache you're talking about? You know, before the I and D units were too far apart?

In article , Flash Gordon wrote: [....]

But if you do that, you loose the ability to check for overruns. The point was that using pointers makes checking very hard to implement. If you are only returning a 3 or 4 element array, the cost of the extra overhead may be worth it.

It was part of my explaination[1] of why the C language is so horrid. [1] troll

I have to admit it isn't as bad as C++ or Intercal.

In article , Rich Grise wrote: [...]

Actually, it may be able to fetch more than one depending on the instruction bus width and the instruction length.

In article , snipped-for-privacy@yahoo.com wrote: [...]

Are you counting number of models or number of units sold here? The 8051 and the PIC are both HA and there's a whole lot of them out there.

Erk sorry.. the 8051 is indeed Harvard. Now I see why you are complaining. I've always hated that beast.

Well.. both, though I'm not sure if the 8051 surpasses everyone else in number of units. Anyone have the numbers? For the purpose of the discussion above the PIC is more RISC-like than CISC-like especially in terms of not having multiple instruction sizes. PICs are all one instruction per cycle affairs (except of course for jumps) with a 2 stage pipeline (the two cycle execution of jumps is due to bubbles). PIC, AVR and MAXQ are good examples of what I'm talking about - RISC (or RISC-like) Harvard CPUs with constant instruction size.

Er, the 8051 is very definitely Harvard old chap.

Ian