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Re: VON NEUMANN VS HARVARD


single memory space
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Keep in mind not all CPUs look like x86. Most pure Harvard machines
like the PIC and AVR and some Von Neumann CPUs (PowerPC I believe?)
have built in bit set/toggle/clear instructions and can do it in
hardware in a single instruction cycle - far less wasted instructions
and much more nifty. Besides, bit read-modify-write is done on the data
memory, nobody's touching the program memory, so it doesn't matter if
it's Harvard or Von Neumann - both behaves the same and if the
instruction sets are similar requires exactly the same amount of
instruction codes. So what exactly are you talking about?


Re: VON NEUMANN VS HARVARD



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The one with the two busses can fetch the next instruction while it's
executing the first one, simultaneously. Nowadays, with these insanely
fast processors, it's pretty much unnecessary with all that queueing
going on.

Cheers!
Rich



Re: VON NEUMANN VS HARVARD


snipped-for-privacy@example.net says...
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The problem is even more severe _because_ the processors are so
much faster than memory.  Modern processors fetch more than one
instruction from memory (memory is fetched in cache line
increments) at a time anyway, Harvard isn't needed for that.

--
  Keith

Re: VON NEUMANN VS HARVARD


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Agreed but Nico was saying that the one with the single bus is faster.
What I'm saying is, even granting him that his instructions are cached,
it will only make it just as fast as a Harvard machine. I don't see how
he can say that Von Neuman machines are faster "because" of the unified
memory space.


Re: VON NEUMANN VS HARVARD


[...]
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Actually, it may be able to fetch more than one depending on the
instruction bus width and the instruction length.
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Re: VON NEUMANN VS HARVARD



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There is a limited number of instruction codes which can be executed
in one cycle. For each memory space, extra instructions are required
to access it (move, test, add, substract, etc). This leaves less room
for other instructions and may force the designer to make some
instructions longer (which will take 2 or more cycles to fetch and
execute).

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Re: VON NEUMANN VS HARVARD


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For each memory space? You only access data in data space, you don't
access data in instruction space (well, on a Von Neumann machine you
can of course). No extra instructions are required. On pure Harvard
machines, jumps, branch and gotos only operate in instruction address,
read/write data access only operate in data address - actually, just
like a Von Neumann machine except instruction and data address are
separate. And most Harvard CPUs are typically also RISC CPUs - they
only have a single instruction size. I have personally never seen a
Harvard CPU with multiple instruction sizes, can you show me one?

Because the data and instruction memory are seperate CPU designers can
use different sizes for them. This allows Harvard machines to *always*
be able to be designed as a single-instruction-per-word RISC machine.


Re: VON NEUMANN VS HARVARD


[...]
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Are you counting number of models or number of units sold here?  The 8051
and the PIC are both HA and there's a whole lot of them out there.


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Re: VON NEUMANN VS HARVARD


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Well.. both, though I'm not sure if the 8051 surpasses everyone else in
number of units. Anyone have the numbers? For the purpose of the
discussion above the PIC is more RISC-like than CISC-like especially in
terms of not having multiple instruction sizes. PICs are all one
instruction per cycle affairs (except of course for jumps) with a 2
stage pipeline (the two cycle execution of jumps is due to bubbles).
PIC, AVR and MAXQ are good examples of what I'm talking about - RISC
(or RISC-like) Harvard CPUs with constant instruction size.


Re: VON NEUMANN VS HARVARD


[....]
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I wouldn't characterize the PIC as "reduced" instruction set for the same
reason as I wouldn't say a PDP-8 was a RISC machine.  They are both "very
simple processors" out of the need to keep the number of transistors low.
  

--
--
snipped-for-privacy@rahul.net   forging knowledge


Re: VON NEUMANN VS HARVARD


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Are you kidding me? Every single modern superscalar CPU is internally a
Harvard CPU. x86, PowerPC, Sparc, MIPS, ARM9 and Alpha are
microarchitecturally Harvard, only at the point of memory controllers
do they look like traditional Von Neumann CPUs. What do you think the
separation of icache and dcache is all about? It's about performance:
being able to decode the next istruction while manipulating the current
data. It's about being able to fetch and commit data and instructions
simultaneously.

C has absolutely no problem with Harvard architecture. In fact, C does
not fully support Von Neumann and the C runtime is designed as a
Harvard machine. Tell me where in the C standard does the language
allow you to write self-modifying code. There are some system calls
that allows you to load data (for example, from a file stream) into the
instruction stream/process table. Exec is an example. But such
functions are not covered by the C standard and is NOT part of the C
standard.

Pure Harvard CPUs like the PIC and AVR have supported C for a long
time. In fact, the AVR was not only designed specifically to support C
but was designed with the input of C compiler writers/developers. I
have 5 C compilers designed for pure Harvard machines so don't tell me
that C "doesn't like" Harvard. OK, yeah the PIC is difficult to write a
compiler for but not because or the Harvard architecture but the
convoluted memory map. The AVR was designed from the ground up from the
point of view of the C compiler.


Re: VON NEUMANN VS HARVARD



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Certainly the internals of these ar harvard, to the external world they
are Princeton.  The L2 caches and bus controllers of all of these
processors are classic Von Neumann.  Self-modifying code can be an issue
though.

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No, the seperate I and D caches are all about simplicity, thus
performance.  The I-Caches can be relatively simple since they can only
have one write and one read port and snooping isn't an issue.  D-Caches
are far more complex and L2s even more so.  Simplicity => fast.

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Where does it not allow this?  OTOH, who cares?

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--
  Keith

Re: VON NEUMANN VS HARVARD


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Actually Yes. And yes you are also right. The speed gain achieved
through simplicity mainly affects three or more operand instruction
sets. For single and double operand instruction sets the dcache will
only need one read and one write port. Well, double operand in terms of
one read and one write. Of course an accumulator based two operand
instruction set may require two read ports.

The first significant gain of separating dcache and icache is that you
can now achieve a one instruction cycle per clock cycle execution
because you are no longer constrained by having to multiplex between
instruction access and data access on the same bus. This affects even
single operand machines. The second gain is as you stated for
multi-operand CPUs the reduced complexity of the icache allows for
faster execution.

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Neither the original K&R C nor C89 nor C90 nor C99 allows you to modify
your source at run time. There is no "eval" function in C or anything
similar which allows you to touch the instruction stream
programatically.

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I was responding to Nico's statement:
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which in my opinion is false since C virtually *assumes* a Harvard
architecture in the language specs. By this I mean that C doesn't
support the main extra feature of a Von Neumann CPU: being able to
access your instruction stream. C doesn't allow that.


Re: VON NEUMANN VS HARVARD


snipped-for-privacy@gmail.com says...
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No, the D-caches must be multi-ported for a number of other
reasons.  At least two ports (read/write) are needed for load/store
operations and two more for the L2.  Of course there may be more
than one load/store unit (and D-Cache ports to go with them) as
well.  The I-cache doesn't need the write port for the load/store
nor the read port for the L2.

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How do you propose to load the D-Cache?

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No, this can be done with a shared cache (and was for years) but
the number of ports, thus the complexity goes up.
 
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Source?  That's syntax.  There is nothing preventing you from
writing anywhere in memory.


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How does it disallow it?  Instructions aren't tagged any
differently than data.  Well, they are in some architectures but
that's not reflected in the language.  ISTM that if C disallowed
executing data there wouldn't be all the stack overflow holes in
Windows we see.

--
  Keith


Re: VON NEUMANN VS HARVARD


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Not for single operand CPU. You just need a single read/write port
because no instruction can both read and write at the same time.

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By loading it? I don't understand your question.

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Of course it can. But before people tried doing it with shared cache it
was already been done as separate I and D cache. In part becasue in the
olden days multi port memory chips were rare and expensive so the main
reason was to be able to fetch data and instruction at the same time.

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Ah but writing "code" like that is not really C is it? It is writing
direct machine code (which is even lower than assembly programming).
That is way outside the scope of the C language and is highly
platform/compiler/implementation/CPU specific.

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OK disallow is probably the wrong word. It doesn't support that. If you
want this sort of thing you have to write the machine code yourself and
pack it in some data in your C program. The compiler won't do it for
you. Scripting languages on the other hand often allow you to write
self-modifying code and is supported directly by the language.

  # Tcl example:
  # This function will return 1 only once and then
  # modifies itself to always return zero:
  proc once {} {
    proc once {} {return 0}
    return 1
  }

but regardless of weather it allows or not the C language is perfectly
happy with the Harvard architecture. It is only when you try to go
outside the C language and directly write hand-assembled
binary-machine-code to the instruction stream will there be a
difference between Harvard and Von Neumann machines. Nico's statement
is still wrong.


Re: VON NEUMANN VS HARVARD


snipped-for-privacy@gmail.com says...
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commit
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Baloney.  You need a write and a read port for the processor and
another set for the L2/bus.  Just because one instruction can't
read and write at the same time doesn't mean there is only one
instruction executing.  Time multiplexing ports is still creating
ports, and complexity.

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You have a read and a write port for the processor.  How does the
data get into the cache?  A: Two more ports (at least).

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Actually it was done that way before because the I and D units were
too far apart.

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Harvard
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Using that definition, one can't even write self modifying code in
assembler either.


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Your definition makes "self modifying code" a useless term.

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Ok, so a language must be interpreted to allow "self modifying"
code.  Strange definition.
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I didn't say he was right.  ...and I still don't like C.  ;-)

--
  Keith

Re: VON NEUMANN VS HARVARD


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Bullshit. I have a Pentium2 motherboard that uses simple SRAMS as L2
cache. Those chips only have a single read/write port (I would know, I
salvaged them when my mobo died). Caches, even today, are not usually
multiported. Don't know about newer chips but even as late as the
Pentium3 the cache is not multiported.

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Not necessary (this proven by the fact that in the real world caches
are in fact single ported). You only load cache when there's a cache
miss (or predicted cache miss). When a miss happens the data is not
available anyway so instruction processing is temporarily stalled or on
threaded CPUs switches to a thread that doesn't stall.

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When? Caches were single ported on most CPUs up to 2001. And on most
CPUs they are still single ported to this day, at most they have
separate read and write port. What CPU implements this massively
multiport cache you're talking about? You know, before the I and D
units were too far apart?


Re: VON NEUMANN VS HARVARD



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No you don't.  PIIs had the L2 on the backside of the bus, on the
cartridge. The original Pentiums (socket 5/7) had SRAMs on the board.

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You are *SO* wrong.  
 
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You'd better study Computer Architecture 101 a bit harder.

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1960s.


Nope.


All current High-end CPUs.

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At least S/370 ->

--
  Keith

Re: VON NEUMANN VS HARVARD


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Then tell me why I need pragma's and non-C extensions when writing C
code for Harvard CPUs to tell the compiler where the data should be
stored & fetched?

--
Reply to nico@nctdevpuntnl (punt=.)
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Re: VON NEUMANN VS HARVARD


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You don't need any pragmas. I've never needed any pragmas when using
the following compilers:

1. AVR gcc
2. HITECH C
3. Keil
4. CC5x
5. CSS

So, what compiler are you using and why do you need those pragmas? I've
only ever needed pragmas for storing data when using a Von Neumann CPU:
the 8051.


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