IR specs the case-to-sink thermal resistance for their TO-220 MOSFETs at 0.5 degrees-C/W. I was trying to do some thermal calculations for TO-220 FETs from other manufacturers and none of them list the case-to-sink resistance.
Is it safe to assume that the 0.5 degrees-C/W value is pretty universal? Or can there be a big difference from manufacturer to manufacturer? The footprint is the same so I'm thinking it's all up to the internal construction/layout. I'm hoping that's pretty well standardized. :-)
Rth case to sink is affected by mounting method (eg screw torque or clip pressure), case surface dimensions, intervening material and heatsink surface finish.
There should be no significant difference between mfrs for similar TO220 package shapes, given a standard plated copper base.
Variations in TO3 are more common, as these can differ in physical construction and base material/rigidity.
Hi John, You're right, I've seen some huge differences in theta_jc out there!
With all of IR's TO-220 FETs having the same theta_cs, 0.50 degrees-C/W, could I assume that other manufacturers have about the same theta_cs (assuming same size base plate, etc., as legg mentioned)?
Right. Theta_cs is arguably zero, in the case of a zero-thickness gap between the transistor and the heat sink. In any case, the semi manufacturer has no right to spec this.
So what is a poor guy like me do to figure out the (rough, theoretical) difference in junction temperature rise between two different FETs in the same application. Ignore Theta_cs?
I'll be putting both to the test and measuring actual case temperatures but wanted a way to narrow down the choices and select the best FET for the app to compare to the one being used now (assuming all other specs fall into place and it's just thermal resistance differences being compared).
You're right. It is just about thermal resistances. The only issue is
*which* resistance parameters need to be considered. Something called Theta_cs implies that they're talking about the interface characteristics between the case of a device and its heatsink. This is up to the designer and NOT the part manufacturer because it's out of their control.
To calculate the die temperature you need to know the power dissipated by a device (of course) and the thermal characteristics between the die and the ambient air.
You typically start with Theta_ja. With this, you are given the temperature rise from the ambient air to the die (per watt). If this indicates that your die will be too hot, for your power level, then you must go further.
If you need to go furher, the next step is using Theta_jc. This indicates the temperature rise from the device case to its die (per watt). You'll, then, need to find a heatsink (whatever its form) that has a low enough Theta_sa (rise from ambient air to sink) to meet your max die temperature requirement, but you'll have to also include the usually-small extra rise you get from the interface between the heatsink and the device case (Theta_cs). Note that this heatsink may be in the form of the pcb mounting itself and/or a true external heatsink.
Bob
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Rth case to sink can be spec'd when the interface and mounting screw type/torque are also included. This was typical in Motorola, RCA, Philips and TI power app notes (mounting instructions, heatsinking), but not so common in part specifications.
For part specs, Rthjc and Rthja are more common, as they do not rely on unlisted factors.
For TO220/SOT186/SC45, direct screw mounting can vary from 0.5 to 1.4, depending on whether or not silicon grease is present. A properly dimensioned and installed spring-clip is supposed to be able to reduce this to a minimum of 0.3 (according to the spring clip mfr...).
Adding an insulator also adds material dependance.
It also depends on the size of the chip. A small chip uses only a small part of the available tab footprint to transfer heat, with farther-away heat conduction limited by lateral spreading within the tab. So there's no single number.
Another issue is that heat sinks may have substantial spreading thermal resistance, too. So the theta of a heat sink can be a lot higher than expected if the heat is applied in one small area, as opposed to distributed uniformly across its surface. A copper heat spreader slug can work wonders.
This is not a "lumped" problem, but a distributed one. So simple math doesn't work very well.
Yep. It's a difficult problem. I needed to deal with one of these "distributed" type heatsinks. It was a thin plate connecting to several FPGAs (what a BITCH!) and eventually a larger extruded heatsink. I tried a couple different methods to estimate the dT/dxy, but I wasn't convinced that they were accurate. I ended up just doing some measurements. It proved that the heatsink plate was very ineffective on its own, so I had to add a heatpipe along its length to get the delta T down to an acceptable level from the far end to the cool end.
Heatpipes are cool devices.
Bob
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Okay, so it seems you're showing the temperature rise of the material above ambient as a function of distance D from the heat source. I've never seen it done that way, but it certainly demonstrates (with simple measurements) the ineffectiveness of the thermally-resistive material as it gets far from the heat source.
I'm sure you've had a chance to play with heat pipes. I was amazed at their performance. I took two of them and cut the end off of one. I put both of them (uncut end down) into a cup of very hot water. The cut one was barely warm at its other end. The good one almost burned my fingers. Very impressive!
Bob
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You may be able to measure the thermal resistance. Now I've measured die temperature doing the following.
1) find a diode on the device
2) feed the diode, forward biased, with a low current, maybe 10ua to
100ua. What you don't want to do is heat up the diode.
3) using an oven, measure the forward drop of the diode versus temperature at various temperatures.
Using table lookup and some interpolation, you can now estimate die temperature IF you can forward bias this diode while the device is operating. Now for a power fet, this is tricky, I suppose you could forward bias the body diode to heat up the device, measuring V and I to compute P.
Maybe I'm close here, but no cigar. On a chip, this scheme works well because you have more pins to play with. You do need to keep the current low to avoid spewing carriers into the substrate. Not use for latch-up, but you can also effect the operation of the device.
The TO220 mounting base IS a copper heat spreader, with a surface contact area more than three times larger than any chip that can be mounted on it and still be properly sealed within it. The thickness/area ratio is actually quite large, allowing very little deltaT across it's surface. This is demonstrated in most models for the package, and is evident in practical thermal imaging trials.
The chip size does not affect the thermal impedance between the heatsink mounting surface and the TO220 body contact area, only the thermal impedance between the junction and the TO220 body contact area (ie Rthjc).
Thermal calculations for semiconductor mounting may require attention to many factors, but answering the OP's question doesn't, in this case.
Depending on how you measure it, namely the pattern in which the heat is applied.
only the
It's all one system. Imagine that the TO220 tab and a big flat copper heat sink were perfectly welded into a single piece of copper, a plane with a pedestal on it, and a small chip generates heat on the TO220 part. Obviously there would be a thermal spreading pattern, sort of hemispherical isotherms in onion shells away from the die, and obviously it would be hottest near the chip and cooler farther away. So the "TO220" part of that structure would not be isothermal.
On can assume the tab is isothermal only if the tab to heatsink interface has high enough theta to swamp the spreading resistance of the tab.
As the die gets smaller, theta goes up, without limit. The TO220 base is obviously not isothermal when the heat is applied as a tiny dot.
It's a matter of perspective and relative real dimensions. Obviously, as one dimension increases the impedance in that dimension will increase. One must also not confuse transient with steady-state conditions.
A good conductor will, at a uniformly poor interface, tend to show uniform temperatures across it's surface.
The venerable Motorola AN1040 appendix B p18 would seem to argue your point - illustrating, as it does, various attempts to produce an accurate 'spot' measurement of a TO220 tab, to develop Rthjc figures. The point is that, depending upon various distortions introduced, one method may be more accurate than another in a particular situation, as the effective length of the path of heat transfer is manipulated (or corrupted, as I might more accurately describe it).
I honestly have been unable to generate temperature differences across the length of a TO220 tab that exceed the bounds of measurement error, using light gauge thermocouples, but then I'm usually measuring in very noisy environments. Body distortion has not been an issue since clips started replacing screws (for completely different reasons). When I do see signifigant variation, I'm more likely to look for the source of measurement error than anything else.
The TO220 was historically the worst choice to defend simple uniformity of the interface, as it so seldom WAS uniform, in practice. Even the reference to the effects of uncontrolled residual Rthja path on these measurements in the app note belie the methods and materials used - admittedly for the sake of simple and practical convenience.
Perhaps my own generalizations are formed from similar motives.
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