transmission line z

But not buried stripline. Once you put your conducting trace between two ground planes, your electric fields are confined, and well defined.

Buried strip-line does lend itself to relatively low impedance structures, and you might realise your transformers as transmission line transformers, with a pair of low impedance strip-lines combining to create twice the voltage swing in a higher impedance output strip line.

Hard to probe, but you could put in occasional vias to make the inner workings visible at crucial points.

Am 08.06.2025 um 22:08 schrieb Leo Baumann:

It is necessary to determine the effective material permittivity of the geometry.

OK. It's easy enough for me to mentally model the stripline as a complexly constructed capacitor.

Open question: Is it possible to view the stripline as unterminated long wire antenna with a length longer than one or two wavelengths? In this case the radiation pattern's major lobe constricts to increasingly align with the antenna axis.

Danke,

With inductance.

People don't usually include radiation in calculating transmission line behavior, even though some geometries probably do radiate. I'd expect that copper and dielectric losses are a lot worse than radiation, and we usually ignore them too.

Stripline between ground planes shouldn't radiate, at least into free space.

Some really fast txlines have serious losses, like later gen PCIe and such. They need adaptive equalizing.

I was at the microwave show in San Francisco yesterday. A guy from R+S was demonstrating an ADC chip that digitizes at 64 Gbps and 12 bits. It connects to an FPGA over *eight* microstrip/CPW lines using the JESD204 protocol. I was shocked. (The chip is too hot to touch and he wouldn't tell me the price.)

I meant 64 G samples/sec. Just run a wideband antenna into the ADC.

I'm having to do some EM simulations at the moment for some fast stuff (13ps rise time) so thought I'd also check the accuracy of that equation I gave.

Although it agrees with the one posted by Leo Baumann from his reference book (for sensible trace widths and heights) the impedance it calculates is nowhere near that given by simulation. If I do a parametric sweep on the width of the return conductor, by the time it's x10 or so that of the trace conductor the resulting impedance agrees with that given by the likes of the Saturn toolkit, or the website linked to by Don, so my simulation is probably correct.

If I have time I'll bend some copper tape over some Kapton tape and cut off a few slices of varing widths to do a TDR measurement on as a reality check.

Where do you get a 13 ps rise time?

Nothing unusual there. That's typical for 28Gb SerDes (it's more like