TI Bulk Acoustic Wave (BAW) clock oscillator

Do only stupid people want to measure time intervals?

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Far from it. But digitising a sawtooth would be a remarkably clumsy and round-about way of doing it.

The simplest option is to count the transitions of a clock waveform. You can get fast and stable clocks. Sometimes you want to interpolate between clock edges, so you could set up pairs of overlapping ramps that cover successive clock cycles and sample the smooth bit of the ramp within a particular clock cycle.

There's a long history of variations on that theme

If each ramp runs for longer than the clock cycle, one of the two will offer a smooth bit that's worth sampling.

This turns out to be a poor approximation to sampling the in-phase and quadrature versions of a stable sinusoidal clock. You have to use a look-up table to convert the sampled voltage into a linear time signal, and you have to pick the waveform which was moving fastest at the sampling instant (but the amplitude tells you that).

Look up tables weren't an item when people first started making this kind of kit, but they have been around for few decades now.

It's much easier to make in-phase and quadrature versions of a smooth (and very nearly ideal) sinusoid than it is to make comparably good ramps.

You can even stick the sinusoids through rather carefully constructed filters to get reduce any harmonic content but the risk is that they won't be in quadrature when they come out.

It takes a while to reduce the concept to it's simplest and easiest to implement form, and even longer to persuade customers that the more obvious solutions aren't as good.

Somebody who peddles a clunky and complicated (but easier to explain) product is evading their educational responsibilities.

But it's hard to count a THz clock.

That's what I said, digitize a sawtooth. You may call it a ramp if you prefer.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

It used to be hard to count a 10MHz clock. Many years ago I refereed a paper that tried to use a string of TTL ripple counters to count a frequency higher than they could handle. The corrected version of the paper used a bunch of LS TTL synchronous counters that were fast enough, and that did get published.

TTL essentially ran out of puff at 50MHz and in the late 1980's I was using 100k ECL to get to 200MHz. ECLinPS got to 500MHz in the early

And what I went on to say - and you snipped - was that this was a step along the path to doing it right.

You are just another paddle-wheel enthusiast who doesn't like screw propellors.

I used a bunch of cml logic, 35 ps stuff, in a recent project. Just in places, because it's expensive.

Envision a fast ramp driving two 35 ps comparators, driving a 35 ps flop, making pretty short pulses. I knew you wouldn't approve.

This board has, basically, 16 ramp timers on the back side, maybe 10 ps usable resolution.

GaN is wonderful for fast power stuff. So are interns.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

What's the application? The devil is always in the details.

Back in the late 1980's I used Gigabit Logic's GaAs parts when I needed the speed and there wasn't any other way to get it. They never could never get the part yield up to a level that made them commercially attractive, so that was a serious error. ECLinPs was almost as fast, but it wasn't around until a few years later.

Until the ramp timers start interfering with one another. They do seem to have an intense desire to communicate amongst themselves.

That's what customers are for.

In Cambridge it took a while to get them up to speed - most of them had been indoctrinated into thinking that their course work had been state of the art, when it has been kept simple enough to let projects fit inside an academic term.

I wasn't much concerned about the vernier ramps talking to one another, but I was concerned about crosstalk inside the Efinix FPGA.

So I built a proto board and tested that, using both applied signals and four PLL'd pseudo-random generators inside. I saw no crosstalk, at picosecond resolution. Not bad for a $9 FPGA.

The real question about customers is, do they come back?

I have a couple of awesome kids for the summer.

A nearby university has senior "capstone" projects, teams of kids who do an 8-month-long project together. We plan to sponsor one. It's not only cheap engineering, it's a way to meet smart kids about to graduate.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Digital signals do have relatively big swings and high thresholds.

Ramps/sawtooths are analog waveformers and littlw wiggles are more pf a problem.

The cheap engineering part is the problem. When I was doing my Ph.D. I was acutely aware that the research I was doing was being done as cheaply as possible. My father had to pay the graduates working in his lab a whole lot more, and his bosses were happy to have him spend a whole lot more than that to let them get stuff done a whole lot faster.