TI Bulk Acoustic Wave (BAW) clock oscillator

:)

So the primary dev. platform isn't the test rig. That's good, sounds like normal practice.

Absolutely! Love the PIO state machines, set myself a little exercise to implement my bespoke RS485 bus protocol in one.

That wouldn't have gone down well in my applications.

We implemented a sorta goofy SPI interface with a state machine.

There is a single line of c code, maybe a macro, that sets a port pin high. Another opcode sets it low. If you do a bunch of hi/lo ops inline, the port pin changes state every 7 nanoseconds. At 200 MHz, that will be 5 ns.

Not bad for 75 cents.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Any analog oscillator needs an amplitude stabilizing mechanism. It needs enough gain to make an exponentially increasing envelope, and then it needs a gain control mechanism to keep from railing.

In your audio oscillator, the AGC loop could be pretty slow. In an instant-start oscillator, one that we want to phase lock to an XO (but keep the trigger time alignment), we need to flatten out the amplitude fast, so we can observe it and phase lock to the xo before it drifts much.

This lock loop is really interesting. I guess it's actually an out-of-phase-locked-loop.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

It's also unnecessary. The obvious answer to your problem is two instant start oscillators, one of which waits for a start pulse for - say - a 1.1 millisecond while the other is being phase-locked to your crystal oscillator by adjusting the bias on - say - a varactor diode for some 0.9 miliseconds. That bias voltage is locked for the next 1.1 millisecond while that oscillator is waiting for the start pulse, and the other oscillator is being disciplined.

It is messy, but it would work. For longer timing intervals you could let the phase-locked loop resume stabilising the timing oscillator as slowly as you liked.

That would kinda work, but as you say is messy.

If we use two oscillators, on alternate triggers, the delays would be a little different, and the alternate-trigger delay will be perceived as jitter.

And we have trigger rates over 10 MHz, so a millisecond-range loop never gets to lock.

The HP 5359A Time Synthesizer used a sorta similar scheme. A delay-line oscillator ran continuously and was phase-locked to an XO. At trigger time, they quenched the oscillator for 75 ns and then restarted it. After that, they used a hetrodyne system to keep it locked to the xo, which took microseconds to lock.

That worked, but it had a lot of insertion delay, mediocre jitter, and low rep rate. And was complex.

The good thing about vintage gear like the HP that the manuals had theory of operation and schematics. Hardly anybody does that any more.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Here's another DDG architecture:

Use an XO to generate quadrature triangle waves. When an external trigger comes in, fire two sample-and-holds to freeze copies of the triangles.

Then two comparators in the obvious places. Select the best comparator output. That is a clock with XO frequency but trigger timing. It works with sawtooths too.

I built one once and it worked OK, but like several other DDG architectures it needs a zero-drift sample-and-hold, and working around that is messy.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Except that if they are consistently different (and in fact there's no obvious reason why they would be different at all) it would be easy enough to build in a correction).

You have to measure it from time to time and keep the correction up-to-date, but that's what computers are for.

Your phase-locked scheme didn't start phase-locking until 10usec into the timed delay, so trigger rates over 10MHz clearly weren't a major part of your business.

And there's no reason why you couldn't use one oscillator to handle all the delays required for a whole millisecond, and then switch over to the other oscillator while you corrected the oscillation frequency of the first oscillator for 900 microseconds.

Long delays would call for a more flexible swapping schedule.

All the time delay systems I've worked on have been complex, and none of them were good for a more than 10MHz rep rate. Save your fantasies for your publicity puffs.

If we re-did the HP 5359A Time Sythesizer today we could do much better, but I'm pretty sure that there are now better ways of doing the job.

Most of the stuff that gets posted here skips the theory of operation too. It takes work to put together something plausible, and some people can't manage it.

The good thing about HP gear was that it was good - it wasn't good because it was vintage, but because Hewlett and Packard hired good people and insisted that they do good work. There was a lot of vintage gear that was total rubbish, and people don't remember that (and actively try to forget it).

Sure high rates are good business. The triggered oscillator runs ungoverned until the PLL kicks in, so that mode needs to be good too. That's why we need a very good LC oscillatot.

That would work, but is complex and expensive, and has differential delays for the two paths, a further complication.

But we do it.

Yes. They didn't have fast ADCs or DACs or FPGAs. Given that, the HP stuff was impressive.

Packard's book, The HP Way, is worth reading. Then read Carly's book.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Generating truly triangular waves (or sawtooths) is impossible

Why not just generate two good sine waves in quadarature in a ring oscillator? A couple of the precision sine wave generators in the low distortion sine wave thread did exactly that because it gives you better sine waves.

Sample and hold the in-phase and quadrature sine waves when the trigger come in - pay attention to the one that's closest to the midline (because the waveform is moving fastest there) and use the other to work out the phase.

Count the zero-crossings to work how many cycles between triggers.

Just digitising the waveform samples and holds it. It needs two good A/D converters - and fast ones if you want a fast clock.

They don't need to be especially good. Think about it.

A delay generator should have crystal oscillator accuracy.

Once it's digitized, what do you do with the data? And how long will that take?

Digitizing the sawtooths can make a nice time-interval counter.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

But a different business.

Or two less good ones that get disciplined every millisecond or so

The whole game is complex and expensive. If the different delays are real, they can be measured and corrected.

To your own satisfaction.

Why read Carly's book? There are lots of ways of screwing up a company and none of them are interesting. I haven't read "The HP Way" and I'm not likely to read that either.

"For example, a comprehensive internet browser was invented in 1993 by HP engineer Ira Goldstein, but executives were unable to see the future importance of browser technology, and the program was cancelled. Instead, Netscape seized the majority of browser market share in 1994–1995."

I have. You don't seem to have.

You can lock that kind of oscillator to a crystal. You've got one feedback loop to stabilise the amplitude and you can thrown in a second one, feeding back a quadrature signal, to stabilise the frequency. I've simulated such a double-stabilised circuit in LTSpice and it seems to work perfectly happily. It used two AD734's which are now hideously expensive. Cruder gain adjusters would work.

The data gets processed. If you want it to happen fast you'd use one of your magic programmable logic parts. I just stuffed it into ECL logic and got that to do the arithmetic I needed.

Why on earth would you bother?

Because people buy things like that.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Yes, one can add a secondary ADC/DAC to fix the leakage of a sample-and-hold. Stanford Research does that in their 645 digital delay generator.

It is a bit of work and isn't perfect.

I guess a slow sample-and-hold could help a fast one.

In their older DG535, they just let the s/h drift and rail, and adjusted the specs.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

You define yourself by the things that don't interest you.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

I used to have one of those. I don’t think I ever tried to use long delays, but I did notice the relatively poor jitter—250 ps or so iirc.

The P400 is much better.

Cheers

Phil Hobbs

And you define yourself by the stuff you snip without marking the snip. I was clearly more interested than you wanted to admit.

"

"For example, a comprehensive internet browser was invented in 1993 by HP engineer Ira Goldstein, but executives were unable to see the future importance of browser technology, and the program was cancelled. Instead, Netscape seized the majority of browser market share in

How initially good organisations end up getting corrupted is an interesting question. US democracy was never all that impressive and Donald Trump's antics have reduced it to a lethal farce.

That's exploiting the gullible.