Switched Cap ADC Residual Voltage

At least one datasheet, from LT, says its input looks like a resistor to ground, when you load the input with a big bypass cap (i.e., a switched capacitor equivalent). That should suggest a switched-capacitor-to-ground topology, in which case the residual error from a proceeding conversion should be small, and the magnitude of charge required per conversion should be consistent (Q = CV, with C reasonably constant).

I wonder then (and I take it, you're wondering as well) how practical it is to, for instance, just repeat the measurement. Convert the input, discard, convert again, keep value. Move to next mux input and repeat. That should minimize any stored charge error.

You could also strap a "buffer" input to GND or VREF or some other convenient source, which presumably would have a constant-offset error rather than a constant-gain error. This would allow you to use an 8-wide mux for 7 inputs, but still at half the sample rate (set 1 = GND, then read

Tim

It seems to vary a lot. We've seen channel-channel carryover of a couple tenths of a per cent on some uP-integrated ADCs. Even a discrete analog mux tends to bleed a bit of channel N into N+1.

Sometimes we digitize ground, or something we know is small or fairly constant, between channels, to flush things out. Or digitize a critical channel twice, and only use the second sample. This can be important in things like electric meters, where a small undesired correlation can make bad errors.

These ADCs can also kick out a bunch of charge and mess up the opamps that drive them.

Delta-sigmas don't seem to have much internal crosstalk.

You may need to read up on "charge soak". All capacitors "soak up" a bit of charge if you leave them at some arbitrary voltage for long enough, and this leak away relatively slowly if you then change the charge.

The usual Spice model is a couple of small parallel capacitors with big resistors in series with each of the parallel capacitors.

The reality is probably bubbles in the dielectric distorting under force of the applied electrostatic field.

The SiO2 capacitors inside ICs are about the best caps in existance. The ADC issue is probably not DA, it's simple time constants. People are building 16 and 18 bit capacitive SAR ADCs with sub-LSB linearity, which wouldn't work if the caps had much DA.

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John Larkin Highland Technology Inc

Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators

OK, it was bad enough when one person misunderstood the physics enough to try to look wise. Two is my threshold:

No, this is not about dielectric absorption. Not in a 12-bit ADC. This is about what charge is left on the caps just from the normal operation of the ADC, which -- sensibly enough -- appears to depend on the way that each individual manufacturer designed their parts, which means, in turn, that I need to strap on my carbide light and go spelunking in ST's data sheets (it's an ST ARM microprocessor I'm talking about).

It's a tradeoff of sampling time (and throughput specs) vs signal carryover. You'd think that could be fixed with some sort of compensation kluge.

We use the ADCs in NXP ARMs, and they are not impressive. They have channel crosstalk and linearity issues. I suspect that a lot of ARM makers buy IP blocks (USB, ADC/DAC, Ethernet) and sort of shovel them into the chip. A side effect is that their support folks don't know much about those bits.

Q: How much current does the ADC reference take?

A: We don't know.

"Received wisdom", back in the day regarding high voltage CRTs becoming recharged after having been short circuited for some time was stresses in the glass being slowly relieved. How much truth there was in that, I don't know.

And why do think that?

John Larkin thinks that SiO2 is the most perfect dielectric that there is, and thus it can't suffer from dielectric absorbtion. Have you got better evidence, or are you merely suffering from an even more advanced case of masculine intuition?

What's abnormal about dielectric absorbtion? I found out about it the hard way in 1979 when working on a 12-bit ADC - and promptly read all the literature that I could find on the subject, which wasn't quite as easy as it is today.

Why on earth you'd expect ST's data sheets to be all that helpful escapes me. Digital designers don't think about subtle stuff like dielectric absorbtion. Analog designers typically ignore it until it forces itself to their attention.