I distributed the decoupling capacitance in every chips' VCC and GND..., is that correct?
4 layer.Yes, I have dedicated ground and power planes.
3.3 and 5 V I/O tolerant is good point, but... ... does it possible no tolerant between 3.3V and 5V? I remember we have to apply more then 10V or 15V to make MOSFETs breakdown, isn't it?Where? close to CPU and DRAM. Yes, a large decoupling capactitor across the supply rails, but I think due to the complicated GND, we still have to add some L to critical components, right?