Reducing Pulse Duration

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You need an edge circuit, normally done with a small cap in series to the trigger circuit.

Jamie

Series capacitor, pick a size that lets "say 250ms +80/-20%" worth of pulse through, details depend on source and load impedance. diode up from ground for the reset.

The circuit relies on, a slow rise or on with a fast rise on ~reset being faster than than ~threshold, there's fewer transistors between ~reset and the flip-flop so that seems like a safe bet.

What

uS rise and fall times for the input pulse. The 555 would not respond to f ast pulse transitions, your circuit relies on the 555 recovering from RESET while the input trigger remains less than Vcc/3 long enough for TRIG to re spond and trigger, otherwise it would remain locked up in off state. So the phony circuit does require an RC on the pulse input to hope guarantee reli able operation.

It's not a safe bet, the old 555 datasheet used to have a graph of minimum required /TRIG duration required for reliable triggering as a function of t he signal level, it was something like 200ns at voltages near V+/3. The cir cuit shown may possibly give small blip output on the negative input edge t oo.

I expect the minimum /TRIG time is met by the pulse even if the reset is asserted. It would likely be a much smaller time for /TRIG hold after /RESET released, perhaps even negative. Likewise, it is unlikely the leading edge of /TRIG will assert before the /RESET does. In essence the longer delay path internal to the 555 timer would delay the /TRIG pulse relative to the /RESET pulse allowing correct operation.

However, I wouldn't be relying on such undocumented chip features in any design I implement. I'm very surprised the simulation worked but it is not unusual for a simulation to miss such detail oriented problems when a cruder model is used.

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mum required /TRIG duration required for reliable triggering as a function of the signal level, it was something like 200ns at voltages near V+/3. The circuit shown may possibly give small blip output on the negative input ed ge too.

No one would use this design. He needs to split the input pulse into two pa ths: 1) direct to /RST and 2) thru R/C lowpass to /TRIG at RC=1.5us. Then it's no problemo.

as drawn it gets 1 second of trig.

it's not a microprocessor it doesn't need to "come out of reset" it just needs to resume.

from the natsemi data sheet:

Q25 which is responsible for reset needs to turn off, it's a PNP emitter follower that should be fairly fast, especially with a 12V rising edge sucking electrons from the from the base

meanwhile the trig signal needs to go though q7 input buffer and Q8 (half of a differential pair) and Q18 which drives the set input, of the flip-flop. Q18 is saturated, so it will take a while to turn off.

the falling edge is less clear, nothings going to happen until the input goes below 4V but it looks like a slow edge would cause more problems than a fast one.