Poor man's UART

Yes, not only is it possible but I have done it. Way back in 1981 when some printers only came with centronics ports and some c/pm boxes only came with RS232 ports there arose a need for serial-parallel converters.

Some competitors used IM6402 or AY-3-1015 uarts but skimped on the RS232 handshake levels using +5V/0V instead of +/- levels. I skimped on the uart (after all they cost several bucks apiece) and made units with true

+/- handshake levels but a deserializer from penny logic chips.

Photo of the blueprint schematic here:

It does have false start bit detection, i.e. if the start bit is a noise spike and returns to marking by mid-bit time then the conversion does not proceed. In the typical usage with cables only a few feet long data errors never occurred so no parity checking was done.

Let me know if you want me to dig out the notes and explain the logic, it has been a while.

In your case you could skip the deserialising and instead generate a serial version of the trigger byte and test it bit-wise instead of byte-wide at the end of a frame.

piglet

He already corrected himself. He meant to say "start bit".

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Rick C

Nice!

But if ever the response "use a PIC" was appropriate....

(Not that I would actually use one of *those* particularly).

Looks like A CM0 is now $0.76 qty 1.

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John Devereux

I just recalled some material from college called string recognizers. A state machine recognizes the sequence of symbols via a state machine. Rather than store all the bits of the word in a register and examine them *after* the word is recognized, a Finite State Machine (FSM) traverses a number of states until the symbol is accepted or rejected.

I think this would require as few as four bits for a counter and just two bits for the FSM. There would need to be at least two more bits (3 might work better) for the clock divisor to find bit center. State zero is idle, waiting for the start bit. In this state, the baud counter counts any time the input is low and presets when it is high. On the clock counter reaching zero the state advances to one or "run". Now when the counter counts down to zero the input is monitored for the appropriate level on the input depending on the bit count. The bit counter advances each time. If the wrong value is found the state changes to two or "wait" for the counter to max out. On reaching count

7 if the FSM is in "run" mode and the right value is on the input the correct character is found and the FSM enters the "ok" state (stop as in look for the stop bit, not a verb). On bit 8 the input is checked for the stop bit, if not found the bit counter does not increment past 9 and an error is indicated if needed. When the stop bit is found the FSM is reset to "idle", the bit counter is reset to zero and the baud counter is allowed to preset. The detection of the indicated character can be based on any of the above combinations of states and counts.

I don't know exactly how much random logic would be required, but this only takes 9 register bits and one combinational term for the output. A

22V10 has enough bits and likely has enough logic as well. This is not as minimal as an MCU in terms of size, but it is one chip at least! 22V10s are hard to find in truly small packages, but devices like Lattice's 4032 aren't. In a 9 mm TQFP48 they are under $2 at qty 1. Even cheaper if you provide the the 1.8 volt core supply.

BTW, Lattice's home page is getting goofier all the time. The image would not indicate anything like a semiconductor company. I started looking to see if I reached the wrong web site.

Input +-------+ -->>---------| FSM |-------------->>-- Char | Idle | +------->| Run |--------+ | | Wait | | | +--->| OK |----+ | | | +-------+ | | | | | | | | 2 +-------+ | | | +-\--| Baud |

Here is how I did that:

A microcontroller would be smaller and cheaper.

What are you doing to that poor shift register? It's VSS pin is tied into the logic!

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Rick C

Vss is tied to ground by a mere 33ohms, the 4094 will not notice that. I think it is actually a rather elegant byte-wide comparator Chris had made. I shall rememember it!

piglet

I don't get what it is doing. Obviously this is doing something with running the ground current through that resistor, but I don't see how that makes a comparator.

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Rick C

The outputs are loaded by 2.2k resistors in the trigger pattern so all mismatching codes will draw Iss and raise the npn emitter. Only when codes match does Iss fall to effectively zero and the npn conducts and rings the bell.

piglet

Ok, I get it. Thanks.

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Rick C