Non-political, Technical Question, are they still allowed here?

The dV on the gate is what causes the transition through the linear region is it not? Table 8 in the chip data gives switching times. Table 6 gives high and low side on resistance. But since 10 amps is way lower than 30 amps I wouldn't be too concered about power dissipation in the chip provided I wasn't operating the chip outside its spec or close to its limits and provided I'd paid enough attention to any heat sinking requirements.

dV*Q energy? The power dissipation in the chip turns into heat. Make sure it can get out quick enough.

I would take a practical approach. I'd ask myself whether we already have a board with a VNH5019A-E on it and if not is it feasible and/or economic to make a test setup? I might then use a pulse generator to give me control of the PWM unless it's easy to do with the device normally intended to produce the PWM. This would also allow me to easily find out whether or not the switching speed of the signal driving the PWM input is anything to be concerned about. If the chip data says nothing about it then a practical approach may be the only way to be certain.

A single series resistor may be enough. You can then put in a zero ohm resistor if it turns out to be unnecessary.

torsdag den 12. november 2020 kl. 20.34.36 UTC+1 skrev Rickster C:

trollers, what dominates the power dissipation, the dV on the gate capacita nce or the transition through the linear region of the transistor where sig nificant current is being passed while significant voltage is across the dr ain-source?

h peaks of 10 amps. The motor controller is a VNH5019A-E which has one pair of transistors on the controller die and the other pair on separate die in the same package.

FET channel resistance dissipation ends up in the various switching FETs. I 'm wondering where most of the power goes as the 20 kHz switching frequency is approached.

has much impact on the switching speed in the FETs? I would expect there t o be enough buffering in the controller that the FETs were switched quickly enough even with a relatively slow rise/fall time on the PWM signal. I don 't see a spec for rise time on the input.

g circuits and we want to use adequate filtering on the signal lines which will slow the edges. I don't have a feel for how much rise time is ok and h ow much is too slow on this signal.

as far as I can tell the data sheet says specs are for

ontrollers, what dominates the power dissipation, the dV on the gate capaci tance or the transition through the linear region of the transistor where s ignificant current is being passed while significant voltage is across the drain-source?

ith peaks of 10 amps. The motor controller is a VNH5019A-E which has one pa ir of transistors on the controller die and the other pair on separate die in the same package.

e FET channel resistance dissipation ends up in the various switching FETs. I'm wondering where most of the power goes as the 20 kHz switching frequen cy is approached.

ut has much impact on the switching speed in the FETs? I would expect there to be enough buffering in the controller that the FETs were switched quick ly enough even with a relatively slow rise/fall time on the PWM signal. I d on't see a spec for rise time on the input.

log circuits and we want to use adequate filtering on the signal lines whic h will slow the edges. I don't have a feel for how much rise time is ok and how much is too slow on this signal.

trollers, what dominates the power dissipation, the dV on the gate capacita nce or the transition through the linear region of the transistor where sig nificant current is being passed while significant voltage is across the dr ain-source?

The dissipation in the switching transistors has two components. One is the ohmic dissipation in the drain while the transistor is on, which is just t he product of the steady current through the MOSFET and it it's "on" drain resistance. The other is the dissipation during switching, which is the int egral of the product of the declining current through the drain and the inc reasing voltage across the drain, which is briefly a lot higher.

You can always push up up the power disspiated during switching by switchin g more slowly (using less current to charge or discharge the gate-drain cap acitance) or more frequently.

Designers tend to switch frequently enough to get get equal amounts of diss ipation from both sources - you've got to have good enough heat sinking to cope with the dissipation when the MOSFET is fully on, and coping with twic e as much dissipation isn't usually that difficult, but it all depends on w hat you are trying to do.

h peaks of 10 amps. The motor controller is a VNH5019A-E which has one pair of transistors on the controller die and the other pair on separate die in the same package.

FET channel resistance dissipation ends up in the various switching FETs. I 'm wondering where most of the power goes as the 20 kHz switching frequency is approached.

Depends how fast the MOFET get turned on and off. Getting more current out of the driver to get the MOSFET to turn on and off fast means more power d issipation in the driver, but less in the MOSFET.

Plot the current and the voltages, sum the product ofs current and voltage and integrate over a full cycle,.

has much impact on the switching speed in the FETs? I would expect there t o be enough buffering in the controller that the FETs were switched quickly enough even with a relatively slow rise/fall time on the PWM signal. I don 't see a spec for rise time on the input.

The signal driving the controller ought to have much faster transition time s than gate drives to the MOSFETs. If they don't this should be fixed by a fast-switching buffer.

g circuits and we want to use adequate filtering on the signal lines which will slow the edges. I don't have a feel for how much rise time is ok and h ow much is too slow on this signal.

Get out an oscilloscope and look. If you want to protect sensitive analog c ircuits from fast switching edges, make the switching signals balanced pair s and route them close together over ground plane, or stick them on shielde d twisted pair. Slowing down the edge speeds is a desperation move - rarely cheap and always nasty.

I'm mainly at the software side of these, rather than the hardware. But if you have a separate MOSFET driver chip, you can keep the lines from that to the MOSFETs as short as possible, and thus get little noise despite the steep flanks and high currents. The control lines from the microcontroller (or FPGA, or whatever) can have slope control as they are not as critical.